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Fixed srl and shr.
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lvella committed Oct 24, 2023
1 parent eedd604 commit 521407d
Showing 1 changed file with 6 additions and 21 deletions.
27 changes: 6 additions & 21 deletions riscv_executor/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -68,7 +68,6 @@ mod builder {
use std::collections::HashMap;

use ast::asm_analysis::Machine;
use itertools::Itertools;
use number::FieldElement;

use crate::{Elem, ExecutionTrace};
Expand Down Expand Up @@ -123,22 +122,8 @@ mod builder {
ret
}

pub fn trace_regs(&self) {
log::trace!(
"{}",
self.trace
.reg_map
.iter()
.sorted_by_key(|(_, idx)| **idx)
.map(|(name, idx)| {
format!("{name}: {}", self.trace.values[self.curr_idx + idx].u())
})
.format(", ")
);
}

/// get current value of register
pub fn g(&self, idx: &str) -> Elem {
pub(crate) fn g(&self, idx: &str) -> Elem {
self.g_idx(self.trace.reg_map[idx])
}

Expand All @@ -148,7 +133,7 @@ mod builder {
}

/// set next value of register
pub fn s(&mut self, idx: &str, value: impl Into<Elem>) {
pub(crate) fn s(&mut self, idx: &str, value: impl Into<Elem>) {
self.s_idx(self.trace.reg_map[idx], value.into());
}

Expand Down Expand Up @@ -217,15 +202,15 @@ mod builder {
Self(HashMap::new())
}

pub fn s(&mut self, addr: u32, val: Elem) {
pub(crate) fn s(&mut self, addr: u32, val: Elem) {
if val.u() != 0 {
self.0.insert(addr, val);
} else {
self.0.remove(&addr);
}
}

pub fn g(&mut self, addr: u32) -> Elem {
pub(crate) fn g(&mut self, addr: u32) -> Elem {
*self.0.get(&addr).unwrap_or(&Elem::zero())
}
}
Expand Down Expand Up @@ -585,8 +570,8 @@ impl<'a, 'b, F: FieldElement> Executor<'a, 'b, F> {
"and" => (args[0].u() & args[1].u()).into(),
"or" => (args[0].u() | args[1].u()).into(),
"xor" => (args[0].u() ^ args[1].u()).into(),
"shl" => (args[0].u() >> args[1].u()).into(),
"shr" => (args[0].u() << args[1].u()).into(),
"shl" => (args[0].u() << args[1].u()).into(),
"shr" => (args[0].u() >> args[1].u()).into(),
_ => {
unreachable!()
}
Expand Down

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