Merge pull request #762 from powdr-labs/fixing-sc

Regression: fixing instruction sc.w
powdr-labs · Nov 9, 2023 · c5d602f · c5d602f
2 parents 12add9b + ee67d36
commit c5d602f
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/riscv/src/compiler.rs b/riscv/src/compiler.rs
@@ -1340,7 +1340,7 @@ fn process_instruction(instr: &str, args: &[Argument], coprocessors: &CoProcesso
             assert_eq!(off, 0);
             // TODO: misaligned access should raise misaligned address exceptions
             let mut statements = vec![
-                "skip_if_zero lr_sc_reservation, 2;".into(),
+                "skip_if_zero lr_sc_reservation, 1;".into(),
                 format!("mstore {rs1}, {rs2};"),
             ];
             if !rd.is_zero() {