mload unaligned.

riscv/src/compiler.rs

@@ -504,6 +504,25 @@ fn preamble(coprocessors: &CoProcessors) -> String {
     instr mstore X { { addr, STEP, X } is m_is_write { m_addr, m_step, m_value } }
     instr mload -> X { { addr, STEP, X } is m_is_read { m_addr, m_step, m_value } }
 
+    /// Loads one word from an address Y, where Y can be between 0 and 2**33 (sic!),
+    /// wraps the address to 32 bits and rounds it down to the next multiple of 4.
+    /// Returns the loaded word and the remainder of the division by 4.
+    instr mload_unaligned Y -> X, Z {
+        // Z * (Z - 1) * (Z - 2) * (Z - 3) = 0,
+        { Z } in { bytes },
+        { Z * 2**28 } in { bytes },
+        Y = wrap_bit * 2**32 + X_b4 * 0x1000000 + X_b3 * 0x10000 + X_b2 * 0x100 + X_b1 * 4 + Z,
+        { X_b1 * 4 } in { bytes },
+        {
+            X_b4 * 0x1000000 + X_b3 * 0x10000 + X_b2 * 0x100 + X_b1 * 4,
+            STEP,
+            X
+        } is m_is_read { m_addr, m_step, m_value }
+        // We could even do the lookup with W instead of X and then:
+        // { W, X, Z} in { shr.value, shr.amount, shr.amount}
+    }
+    
+
     // ============== control-flow instructions ==============
 
     instr jump l: label { pc' = l }
@@ -1183,10 +1202,7 @@ fn process_instruction(instr: &str, args: &[Argument], coprocessors: &CoProcesso
             let (rd, rs, off) = rro(args);
             only_if_no_write_to_zero_vec(
                 vec![
-                    format!("tmp1 <== wrap({rs} + {off});"),
-                    "addr <== and(tmp1, 0xfffffffc);".to_string(),
-                    "tmp2 <== and(tmp1, 0x3);".to_string(),
-                    format!("{rd} <== mload();"),
+                    format!("{rd}, tmp2 <== mload_unaligned({rs} + {off});"),
                     format!("{rd} <== shr({rd}, 8 * tmp2);"),
                     format!("{rd} <== sign_extend_byte({rd});"),
                 ],