Hello and welcome to my 21-day exploration of SystemVerilog! For the next 21 days, this course will enable us to explore various flavors of digital design, starting from basic components like multiplexers to building complex, real-life digital systems. It challenges us to think critically, enhances our problem-solving abilities, and fosters creativity in coming up with efficient design solutions. Each task is designed to deepen our understanding of hardware description languages and how they shape the creation of powerful digital systems.
All of this is done using the Quicksilicon platform and all your tasks can be done here.
- Day-01 Multiplexer
- Day-02 D Flip-Flop
- Day-03 Edge Detector
- Day-04 Simple ALU
- Day-05 Odd Counter
- Day-06 Shift Register
- Day-07 LFSR
- Day-08 Binary to One-hot
- Day-09 Binary to Grey
- Day-10 Self Reloading Counter
- Day-11 Parallel to Serial
- Day-12 Sequence Detector
- Day-13 Muxes
- Day-14 Fixed Priority Arbiter
- Day-15 Round Robin Arbiter
- Day-16 APB Master
- Day-17 Simple Memory Interface
- Day-18 APB Slave
- Day-19 Synchronous FIFO
- Day-20 APB System
- Day-21 [Module which finds the second bit set from LSB for a N-bit vector.]