Synopsis

GAPy (pronounced "Gee - Aee - Pie") is an assortment of Python scripts that FPGA developers can use to automate code development and work flow. These tools are Python3-based only and will not support the old Python2 constructs.

getInstance.py - A script that will parse a user-specified HDL file's port list and parameter list, converting it to a block of code used for instantiation that is accessible from the user's OS Clipboard.

synthesisParser.py - A script used to ease the process of manually parsing the synthesis logfile generated by the synthesis tool, Synplify Pro. It provides a lightweight interactive prompt for navigating the different informational statements in the logfile.

boolean_compare.py - A script that allows a designer to efficiently compare the entire bitfield of two equal-width boolean equations. For now, the equations must reduce to a single bit.

hdl_comments.py - A script will count a files comments and calculate the percentage of lines that have comments to total lines in the file. All flavors of VHDL files will be scanned and have their metrics output to the terminal.

Motivation

FPGA development has a lack of automation tools, to say the least. I intend to change that. This repository will contain a list of functions that will make an FPGA developers coding experience faster and more efficient.

Installation

Clone this project to an accessible location on your local machine or server:

git clone https://github.com/rdustinb/fpga_code_ops.git

The user should run:

python3 getInstance.py --path

to properly add the script to the user's .alias file for future use.

If any dependencies are missing each script will tell the designer how to install them.

Dependecies

The tools in this repository depend on the following Python Libraries:

getopt - allows user input from the terminal to be pulled into the script in a concise manner.

sys - allows Terminal arguments to be enumerated inside the scripts.

pyperclip - allows the scripts to access your systems Clipboard for writing. Don't worry, these scripts aren't reading out of the Clipboard for any reasons.

operator - efficient operators implicit to the Python language.

re - Python-based regular expression libraries. Because everything is easier with RegExps.

math - Python math library needed for the log2 operation.

time - Python runtime library needed to time the operations of the boolean_compare. Will be removed in a future commit.

os - library used to scan folder hierarchies.

termcolor - library that allows text to be colored for printing to the terminal.

Code Example

getInstance path/to/hdl/file.sv <tabSpace> <column align> <comment align>

Where each option performs the following spacing:

module_name #(
                .BUSWIDTH                  (BUSWIDTH),
<--tabSpace-->  .RSTPOL <--column align--> (RSTPOL),
                ...
                .MAGIC                     (MAGIC)
) module_name_0 (
                .clk                       (clk),                          // in [1]
<--tabSpace-->  .ben    <--column align--> (ben),      <--comment align--> // in [15:0]
                ...
                .active                    (active),                       // inout [1]
                .dout                      (dout)                          // out [3:0]
);

I personally use the following command:

getInstance path/to/hdl/file.sv 2 25 15

Both the and options begin counting columns at the port-name-dot . and the port-connect-opening-parentheses (. The three options are additive to an absolute column number. For instance, if the options 2 25 15 are specified, the comments of the ports will begin on column 42 when the instance is pasted into the containing document or code file.

$ python3 synthesis_parser.py

The script currently only dumps data to the terminal. Change the selectedBlockName line from "all" to the full hdl filename to limit the printout.

$ python3 hdl_comments.py -f path/to/file.[sv|v|vh|vhd]

OR

$ python3 hdl_comments.py -d path/to/directory

OR

$ python3 hdl_comments.py -f path/to/file.sv -i `timescale

The -d option can be used instead of the -f option, along with a folder location to have the script parse for all Verilog and VHDL files in the hierarchy from the specified folder down. The -d option takes presedence over the -f option.

With either -f or -d, the -i option can be specified to ignore comment counting up until a keyword is detected in the file. This is useful if all files have a common legal header in the file and you want the script skip over it to then count comments after the header.

Tests

Running any of the scripts with the --test option will cause the script to run using the example code in the tests/ folder.

Contributors

If you have a feature request, please add it! You can follow me on Twitter: @DigitalKrampus

License

I am using the simple MIT license for this repository as I do not intend for this code base to be closed in any way, but I'd like a simple license present.