Fixes for CI

zirgen/circuit/rv32im/v2/dsl/pack.zir

@@ -3,7 +3,7 @@
 
 import bits;
 import arr;
-import po2;
+import u32;
 
 // We have 3 functions here:
 // 1) Pack an array of N bits into N/P elements

zirgen/circuit/rv32im/v2/emu/preflight.cpp

@@ -327,7 +327,7 @@ PreflightTrace preflightSegment(const Segment& in, size_t segmentSize) {
 
   // Now, go back and update memory transactions to wrap around
   for (auto& txn : ret.txns) {
-    if (txn.prevCycle == -1) {
+    if (static_cast<int>(txn.prevCycle) == -1) {
       // If first cycle for word, set to 'prevCycle' to final cycle
       txn.prevCycle = preflightContext.prevCycle[txn.word];
     } else {

zirgen/circuit/rv32im/v2/emu/sha.h

@@ -14,6 +14,8 @@
 
 #pragma once
 
+#include <arpa/inet.h>
+
 namespace zirgen::rv32im_v2 {
 
 // 1 to 1 state from inst_sha

zirgen/circuit/rv32im/v2/test/BUILD.bazel

@@ -1,18 +1,14 @@
 load("@zirgen//bazel/toolchain/rv32im-linux:defs.bzl", "risc0_cc_kernel_binary")
+load(":defs.bzl", "riscv_test_suite")
 
 cc_test(
     name = "test_parallel",
-    srcs = [
-        "test_parallel.cpp",
-    ],
+    srcs = ["test_parallel.cpp"],
     data = [
         "//zirgen/circuit/rv32im/v2/emu/test:guest",
         "//zirgen/circuit/rv32im/v2/kernel",
-        "@zirgen//zirgen/circuit/rv32im/shared/test:riscv_test_bins",
-    ],
-    deps = [
-        "//zirgen/circuit/rv32im/v2/run",
     ],
+    deps = ["//zirgen/circuit/rv32im/v2/run"],
 )
 
 risc0_cc_kernel_binary(
@@ -26,28 +22,9 @@ risc0_cc_kernel_binary(
 
 cc_test(
     name = "test_p2",
-    srcs = [
-        "test_p2.cpp",
-    ],
-    data = [
-        ":test_p2_kernel",
-    ],
-    deps = [
-        "//zirgen/circuit/rv32im/v2/run",
-    ],
-)
-
-cc_test(
-    name = "test_riscv_bins",
-    srcs = [
-        "test_riscv_bins.cpp",
-    ],
-    data = [
-        "//zirgen/circuit/rv32im/shared/test:riscv_test_bins",
-    ],
-    deps = [
-        "//zirgen/circuit/rv32im/v2/run",
-    ],
+    srcs = ["test_p2.cpp"],
+    data = [":test_p2_kernel"],
+    deps = ["//zirgen/circuit/rv32im/v2/run"],
 )
 
 risc0_cc_kernel_binary(
@@ -61,13 +38,18 @@ risc0_cc_kernel_binary(
 
 cc_test(
     name = "test_sha",
-    srcs = [
-        "test_sha.cpp",
-    ],
-    data = [
-        ":test_sha_kernel",
-    ],
+    srcs = ["test_sha.cpp"],
+    data = [":test_sha_kernel"],
+    deps = ["//zirgen/circuit/rv32im/v2/run"],
+)
+
+cc_binary(
+    name = "risc0-simulate",
+    srcs = ["risc0-simulate.cpp"],
     deps = [
+        "//risc0/core",
         "//zirgen/circuit/rv32im/v2/run",
     ],
 )
+
+riscv_test_suite()

zirgen/circuit/rv32im/v2/test/defs.bzl

@@ -0,0 +1,63 @@
+INST_TESTS = [
+    "add",
+    "addi",
+    "and",
+    "andi",
+    "auipc",
+    "beq",
+    "bge",
+    "bgeu",
+    "blt",
+    "bltu",
+    "bne",
+    "jal",
+    "jalr",
+    "lb",
+    "lbu",
+    "lh",
+    "lhu",
+    "lui",
+    "lw",
+    "or",
+    "ori",
+    "sb",
+    "sh",
+    "simple",
+    "sll",
+    "slli",
+    "slt",
+    "slti",
+    "sltiu",
+    "sltu",
+    "sra",
+    "srai",
+    "srl",
+    "srli",
+    "sub",
+    "sw",
+    "xor",
+    "xori",
+    "div",
+    "divu",
+    "mul",
+    "mulh",
+    "mulhsu",
+    "mulhu",
+    "rem",
+    "remu",
+]
+
+def riscv_test_suite():
+    for test in INST_TESTS:
+        native.py_test(
+            # tags = ["manual"],
+            name = test + "_test",
+            srcs = ["run_test.py"],
+            main = "run_test.py",
+            args = [test],
+            data = [
+                "//zirgen/circuit/rv32im/shared/test:riscv_test_bins",
+                ":risc0-simulate",
+            ],
+            size = "large",
+        )

zirgen/circuit/rv32im/v2/test/risc0-simulate.cpp

@@ -0,0 +1,47 @@
+// Copyright 2024 RISC Zero, Inc.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "risc0/core/log.h"
+#include "zirgen/circuit/rv32im/v2/platform/constants.h"
+#include "zirgen/circuit/rv32im/v2/run/run.h"
+
+using namespace zirgen::rv32im_v2;
+
+int main(int argc, char* argv[]) {
+  risc0::setLogLevel(2);
+  if (argc < 2) {
+    LOG(1, "usage: risc0-simulate <elf>");
+    exit(1);
+  }
+
+  LOG(1, "File = " << argv[1]);
+  try {
+    size_t cycles = 10000;
+
+    TestIoHandler io;
+
+    // Load image
+    auto image = MemoryImage::fromRawElf(argv[1]);
+    // Do executions
+    auto segments = execute(image, io, cycles, cycles);
+    // Do 'run' (preflight + expansion)
+    for (const auto& segment : segments) {
+      runSegment(segment, cycles);
+    }
+  } catch (const std::runtime_error& err) {
+    LOG(1, "Failed: " << err.what());
+    exit(1);
+  }
+  return 0;
+}

zirgen/circuit/rv32im/v2/test/run_test.py

@@ -0,0 +1,26 @@
+#!/usr/bin/env python
+# Copyright 2022 RISC Zero, Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import subprocess
+import sys
+
+sys.exit(
+    subprocess.run(
+        [
+            "zirgen/circuit/rv32im/v2/test/risc0-simulate",
+            "zirgen/circuit/rv32im/shared/test/" + sys.argv[1],
+        ]
+    ).returncode
+)