Merge branch 'main' into dependabot/cargo/bytemuck-1.21.0

zirgen/Main/Target.cpp

@@ -1,4 +1,4 @@
-// Copyright 2024 RISC Zero, Inc.
+// Copyright 2025 RISC Zero, Inc.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -14,7 +14,7 @@
 
 #include "zirgen/Main/Target.h"
 
-llvm::StringLiteral licenseHeader = R"(// Copyright 2024 RISC Zero, Inc.
+llvm::StringLiteral licenseHeader = R"(// Copyright 2025 RISC Zero, Inc.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.

zirgen/circuit/rv32im/shared/rv32im.h

@@ -1,4 +1,4 @@
-// Copyright 2024 RISC Zero, Inc.
+// Copyright 2025 RISC Zero, Inc.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -71,7 +71,7 @@
     TblEntry(6, 1, 0x23, 0x1,   -1, SH) \
     TblEntry(6, 2, 0x23, 0x2,   -1, SW) \
     TblEntry(7, 0, 0x73, 0x0, 0x00, EANY) \
-    TblEntry(7, 1, 0x73, 0x0, 0x18, MRET) \
+    TblEntry(7, 1, 0x73, 0x0, 0x18, MRET)
 // clang-format on
 
 namespace zirgen {
@@ -208,7 +208,7 @@ class FastDecodeTable {
 
 // The emulator class is templated on a 'context' object that allows
 // other code to observe the and override various parts of the emulator.
-// We provide a simple base version of this for testing 
+// We provide a simple base version of this for testing
 struct BaseContext {
   bool done = false;
   uint32_t pc;
@@ -231,16 +231,14 @@ struct BaseContext {
 
   // Handle privledged instructions
   bool doECALL() {
-    done = true;  // ECALL induces termination
-    return true;  // end normally
-  }
-  bool doMRET() {
-    throw std::runtime_error("Unimplemented");
-  }
-  bool doTrap(TrapCause cause) {
-    throw std::runtime_error("Unimplemented");
+    done = true; // ECALL induces termination
+    return true; // end normally
   }
 
+  bool doMRET() { throw std::runtime_error("Unimplemented"); }
+
+  bool doTrap(TrapCause cause) { throw std::runtime_error("Unimplemented"); }
+
   // Callback when instructions are decoded
   void instDecoded(InstType type, const DecodedInst& decoded) {}
 
@@ -252,22 +250,16 @@ struct BaseContext {
   void setPC(uint32_t pc) { this->pc = pc; }
 
   // Manage registers
-  uint32_t loadReg(uint32_t reg) {
-    return regs[reg];
-  }
+  uint32_t loadReg(uint32_t reg) { return regs[reg]; }
   void storeReg(uint32_t reg, uint32_t val) {
     if (reg) {
       regs[reg] = val;
     }
   }
 
   // Manage memory
-  uint32_t loadMem(uint32_t word) {
-    return memory[word];
-  }
-  void storeMem(uint32_t word, uint32_t val) {
-    memory[word] = val;
-  }
+  uint32_t loadMem(uint32_t word) { return memory[word]; }
+  void storeMem(uint32_t word, uint32_t val) { memory[word] = val; }
 };
 
 template <typename Context> class RV32Emulator {
@@ -296,7 +288,7 @@ template <typename Context> class RV32Emulator {
       return;
     }
     uint32_t inst = context.loadMem(pc / 4);
-    if ((inst & 0x3) != 0x3) { 
+    if ((inst & 0x3) != 0x3) {
       context.doTrap(TrapCause::ILLEGAL_INSTRUCTION);
       return;
     }
@@ -329,7 +321,8 @@ template <typename Context> class RV32Emulator {
       ret = context.doTrap(TrapCause::ILLEGAL_INSTRUCTION);
       break;
     }
-    if (ret) context.endNormal(type, decoded);
+    if (ret)
+      context.endNormal(type, decoded);
   }
 
 private:
@@ -594,19 +587,19 @@ template <typename Context> class RV32Emulator {
 
   bool stepPriv(InstType type, const DecodedInst& decoded) {
     switch (type) {
-      case InstType::EANY:
-        switch(decoded.rs2) {
-          case 0:
-            return context.doECALL();
-          case 1:
-            return context.doTrap(TrapCause::BREAKPOINT);
-          default:
-            return context.doTrap(TrapCause::ILLEGAL_INSTRUCTION);
-          }
-      case InstType::MRET:
-        return context.doMRET();
+    case InstType::EANY:
+      switch (decoded.rs2) {
+      case 0:
+        return context.doECALL();
+      case 1:
+        return context.doTrap(TrapCause::BREAKPOINT);
       default:
-        __builtin_unreachable();
+        return context.doTrap(TrapCause::ILLEGAL_INSTRUCTION);
+      }
+    case InstType::MRET:
+      return context.doMRET();
+    default:
+      __builtin_unreachable();
     }
     return true;
   }

zirgen/circuit/rv32im/v2/dsl/inst_control.zir

@@ -38,8 +38,8 @@ component ControlResume(cycle: Reg, ii: InstInput) {
     InstOutput(pc, StateResume(), mode.low)
   } else {
     global input : DigestReg;
-    for i : 0..8 { 
-      MemoryWrite(cycle, InputWord() + i, 
+    for i : 0..8 {
+      MemoryWrite(cycle, InputWord() + i,
         ValU32(input.values[i].low, input.values[i].high));
     };
     InstOutput(ii.pc_u32, StateDecode(), ii.mode)
@@ -55,10 +55,7 @@ component ControlUserECALL(cycle: Reg, input: InstInput) {
   load_inst.low = 0x0073;
   input.state = StateDecode();
   input.mode = 0;
-  dispatch_idx := MemoryRead(cycle, UserRegBase() + RegA7());
-  dispatch_idx.high = 0;
-  U16Reg(dispatch_idx.low * 128);
-  new_pc_addr := MemoryRead(cycle, EcallDispatchWord() + dispatch_idx.low);
+  new_pc_addr := MemoryRead(cycle, EcallDispatchWord());
   MemoryWrite(cycle, MepcWord(), input.pc_u32);
   InstOutput(new_pc_addr, StateDecode(), 1)
 }
@@ -98,7 +95,7 @@ component ControlSuspend(cycle: Reg, input: InstInput) {
       // TODO: Apparently if we don't have this clause, the compiler generates
       // a mux where the 'else' case fails at runtime.
     };
-  
+
     // Begin page out
     InstOutput(ValU32(0, 0), StatePoseidonEntry(), 3)
   } else {

zirgen/circuit/rv32im/v2/emu/preflight.cpp

@@ -1,4 +1,4 @@
-// Copyright 2024 RISC Zero, Inc.
+// Copyright 2025 RISC Zero, Inc.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.

zirgen/circuit/rv32im/v2/emu/r0vm.h

@@ -1,4 +1,4 @@
-// Copyright 2024 RISC Zero, Inc.
+// Copyright 2025 RISC Zero, Inc.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -107,11 +107,7 @@ template <typename Context> struct R0Context {
 
   // Generic ecall handling for user mode
   bool doUserECALL() {
-    uint32_t dispatch = loadReg(REG_A7);
-    if (dispatch >= 512) {
-      return doTrap(TrapCause::ENVIRONMENT_CALL_FROM_U_MODE);
-    }
-    uint32_t dispatchAddr = loadMem(ECALL_DISPATCH_WORD + dispatch);
+    uint32_t dispatchAddr = loadMem(ECALL_DISPATCH_WORD);
     if (dispatchAddr % 4 != 0 || dispatchAddr < KERNEL_START_ADDR) {
       return doTrap(TrapCause::ENVIRONMENT_CALL_FROM_U_MODE);
     }

zirgen/circuit/rv32im/v2/kernel/entry.s

@@ -1,3 +1,16 @@
+# Copyright 2025 RISC Zero, Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
 
 .section .text
 .global _start
@@ -12,4 +25,3 @@ _start:
   li sp, 0xfff00000
   /* Jump to kernel start at the C level */
   call start
-

zirgen/circuit/rv32im/v2/kernel/kernel.cpp

@@ -1,4 +1,4 @@
-// Copyright 2024 RISC Zero, Inc.
+// Copyright 2025 RISC Zero, Inc.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -83,13 +83,16 @@ inline void do_poseidon2(uint32_t state, uint32_t bufIn, uint32_t bufOut, uint32
 
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Warray-bounds"
+
 // Helpers to access user registers
 inline uint32_t get_ureg(uint32_t reg) {
   return (reinterpret_cast<uint32_t*>(USER_REGS_ADDR))[reg];
 }
+
 inline void set_ureg(uint32_t reg, uint32_t val) {
   (reinterpret_cast<uint32_t*>(USER_REGS_ADDR))[reg] = val;
 }
+
 #pragma GCC diagnostic pop
 
 // Implement system calls
@@ -139,11 +142,13 @@ inline uint32_t sys_write(uint32_t fd, uint32_t buf, uint32_t len) {
     set_ureg(REG_A0, sys_##name(get_ureg(REG_A0)));                                                \
     mret();                                                                                        \
   }
+
 #define SYSCALL_WRAP_2(name)                                                                       \
   void sys_##name##_wrap() {                                                                       \
     set_ureg(REG_A0, sys_##name(get_ureg(REG_A0), get_ureg(REG_A1)));                              \
     mret();                                                                                        \
   }
+
 #define SYSCALL_WRAP_3(name)                                                                       \
   void sys_##name##_wrap() {                                                                       \
     set_ureg(REG_A0, sys_##name(get_ureg(REG_A0), get_ureg(REG_A1), get_ureg(REG_A2)));            \
@@ -155,12 +160,26 @@ inline uint32_t sys_write(uint32_t fd, uint32_t buf, uint32_t len) {
 SYS_CALL_LIST
 #undef SyscallEntry
 
+uint32_t syscallTable[512];
+
+extern "C" void ecall_dispatch() {
+  uint32_t idx = get_ureg(REG_A7);
+  register uintptr_t t0 asm("t0") = syscallTable[idx];
+  asm volatile("jr t0\n"
+               :         // no outputs
+               : "r"(t0) // inputs
+               :         // no clobbers
+  );
+}
+
 extern "C" void start() {
   // Set up user stack
   set_ureg(REG_SP, 0xbffffffc);
-  uint32_t* table = reinterpret_cast<uint32_t*>(ECALL_DISPATCH_ADDR);
   // Set up syscall dispatch table
-#define SyscallEntry(id, name, args) table[id] = reinterpret_cast<uint32_t>(sys_##name##_wrap);
+  uint32_t* dispatchAddr = reinterpret_cast<uint32_t*>(ECALL_DISPATCH_ADDR);
+  *dispatchAddr = reinterpret_cast<uint32_t>(ecall_dispatch);
+#define SyscallEntry(id, name, args)                                                               \
+  syscallTable[id] = reinterpret_cast<uint32_t>(sys_##name##_wrap);
   SYS_CALL_LIST
 #undef SyscallEntry
   // Jump into userland

zirgen/circuit/rv32im/v2/test/test_parallel.cpp

@@ -1,4 +1,4 @@
-// Copyright 2024 RISC Zero, Inc.
+// Copyright 2025 RISC Zero, Inc.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -22,18 +22,22 @@ const std::string kernelName = "zirgen/circuit/rv32im/v2/kernel/kernel";
 const std::string progName = "zirgen/circuit/rv32im/v2/emu/test/guest";
 
 int main() {
-  size_t threshold = 16000;
-  size_t segmentSize = 16384;
-  size_t maximum = 100000;
-  TestIoHandler io;
-  io.push_u32(0, 5);
+  try {
+    size_t threshold = 16000;
+    size_t segmentSize = 16384;
+    size_t maximum = 100000;
+    TestIoHandler io;
+    io.push_u32(0, 5);
 
-  // Load image
-  auto image = MemoryImage::fromElfs(kernelName, progName);
-  // Do execution
-  auto segments = execute(image, io, threshold, maximum);
-  // Do 'run' (preflight + expansion)
-  for (const auto& segment : segments) {
-    runSegment(segment, segmentSize);
+    // Load image
+    auto image = MemoryImage::fromElfs(kernelName, progName);
+    // Do execution
+    auto segments = execute(image, io, threshold, maximum);
+    // Do 'run' (preflight + expansion)
+    for (const auto& segment : segments) {
+      runSegment(segment, segmentSize);
+    }
+  } catch (std::exception& ex) {
+    printf("Exception: %s\n", ex.what());
   }
 }

zirgen/compiler/codegen/cpp/poly.tmpl.cpp

@@ -1,4 +1,4 @@
-// Copyright 2024 RISC Zero, Inc.
+// Copyright 2025 RISC Zero, Inc.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.

zirgen/compiler/codegen/cpp/step.tmpl.cpp

@@ -1,4 +1,4 @@
-// Copyright 2024 RISC Zero, Inc.
+// Copyright 2025 RISC Zero, Inc.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.

zirgen/compiler/codegen/gpu/step.tmpl.cu

@@ -1,4 +1,4 @@
-// Copyright 2024 RISC Zero, Inc.
+// Copyright 2025 RISC Zero, Inc.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.

zirgen/compiler/codegen/gpu/step.tmpl.metal

@@ -1,4 +1,4 @@
-// Copyright 2024 RISC Zero, Inc.
+// Copyright 2025 RISC Zero, Inc.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.

zirgen/compiler/codegen/rust/info.tmpl.rs

@@ -1,4 +1,4 @@
-// Copyright 2024 RISC Zero, Inc.
+// Copyright 2025 RISC Zero, Inc.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.

zirgen/compiler/codegen/rust/poly_ext_def.tmpl.rs

@@ -1,4 +1,4 @@
-// Copyright 2024 RISC Zero, Inc.
+// Copyright 2025 RISC Zero, Inc.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.

zirgen/compiler/codegen/rust/taps.tmpl.rs

@@ -1,4 +1,4 @@
-// Copyright 2024 RISC Zero, Inc.
+// Copyright 2025 RISC Zero, Inc.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.