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Updates after internal review #8

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2 changes: 1 addition & 1 deletion Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@
# the Doc Template for RISC-V Extensions.

DATE ?= $(shell date +%Y-%m-%d)
VERSION ?= v1.0.0-rc1
VERSION ?= v1.0.0-rc2
REVMARK ?= Draft
DOCKER_RUN := docker run --rm -v ${PWD}:/build -w /build \
riscvintl/riscv-docs-base-container-image:latest
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8 changes: 2 additions & 6 deletions src/bibliography.adoc
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@@ -1,8 +1,4 @@
[bibliography]
== References
== Bibliography

* link:https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0.0/riscv-iommu.pdf[RISC-V IOMMU Specification], v1.0.0
* link:https://uefi.org/specs/ACPI/6.5/[ACPI Specification], Version: v6.5

// REVISIT
//bibliography::[]
bibliography::[]
6 changes: 6 additions & 0 deletions src/changelog.adoc
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@@ -1,5 +1,11 @@
== Changelog

- *Version 1.0.0-rc2*
* Draft for ARC review.
* Addressed internal review feedback.
* Used IEEE style bibliography.
* Allowed HW ID to be valid for PCI IOMMU as well.
- *Version 1.0.0-rc1*
* Draft for internal review.
* Added ID mapping examples.
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1 change: 1 addition & 0 deletions src/contributors.adoc
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Expand Up @@ -4,6 +4,7 @@ This RISC-V specification has been contributed to directly or indirectly by:

[%hardbreaks]
* Aaron Durbin <adurbin@rivosinc.com>
* Andrew Jones <ajones@ventanamicro.com>
* Anup Patel <apatel@ventanamicro.com>
* Atish Kumar Patra <atishp@rivosinc.com>
* Bin Meng <bmeng@tinylab.org>
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9 changes: 5 additions & 4 deletions src/intro.adoc
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@@ -1,6 +1,7 @@
== Introduction

The RISC-V IO Mapping Table (RIMT) provides information about the RISC-V IOMMU and the relationship
between the IO topology and the IOMMU in ACPI based RISC-V platforms. The RIMT identifies which
components are behind IOMMU and how they are connected together. RISC-V IOMMU can be implemented as
either a PCI device or a platform device.
The RISC-V IO Mapping Table (RIMT) provides information about the RISC-V IOMMU
cite:[IOMMU-SPEC] and the relationship between the IO topology and the IOMMU in
ACPI cite:[ACPI-SPEC] based RISC-V platforms. The RIMT identifies which
components are behind IOMMU and how they are connected together. RISC-V IOMMU
can be implemented as either a PCI device or a platform device.
5 changes: 3 additions & 2 deletions src/rimt-main.adoc
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Expand Up @@ -81,8 +81,9 @@ the structure in RIMT used to report the configuration and capabilities of each
by the IOMMU.
| Reserved | 2 | 4 | Must be zero.
| ID | 2 | 6 | Unique ID of this IOMMU.
| Hardware ID | 8 | 8 | ACPI ID. This field is valid only for
an IOMMU that is a platform device.
| Hardware ID | 8 | 8 | ACPI ID of the platform IOMMU device
or PCI ID (Vendor ID + Device ID) for
the PCI IOMMU device.
| Base Address | 8 | 16 | Base address of the IOMMU registers.
This field is valid only for an IOMMU
that is a platform device. If IOMMU
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4 changes: 2 additions & 2 deletions src/rimt-spec.adoc
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Expand Up @@ -3,7 +3,7 @@
:docgroup: Platform Runtime Services Task Group
:description: RISC-V IO Mapping Table (RIMT)
:company: RISC-V.org
:revdate: 9/2024
:revdate: 10/2024
:revnumber: 1.0
:revremark: This document is under development. Expect potential changes. Visit http://riscv.org/spec-state for further details.
:revinfo:
Expand All @@ -23,7 +23,7 @@
//:srcdir: src
:bibtex-file: src/rimt.bib
:bibtex-order: alphabetical
:bibtex-style: apa
:bibtex-style: ieee
:icons: font
:lang: en
:listing-caption: Listing
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4 changes: 2 additions & 2 deletions src/rimt.bib
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Expand Up @@ -3,6 +3,6 @@ @electronic{IOMMU-SPEC
url = {https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0.0/riscv-iommu.pdf}
}
@electronic{ACPI-SPEC,
title = {Advanced Configuration and Power Interface Specification 6.6},
url = {https://uefi.org/specifications}
title = {Advanced Configuration and Power Interface Specification 6.5},
url = {https://uefi.org/specs/ACPI/6.5}
}