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Add a note for ILP32E #257

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Add a note for ILP32E #257

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4 changes: 4 additions & 0 deletions riscv-cc.adoc
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Original file line number Diff line number Diff line change
Expand Up @@ -260,6 +260,10 @@ boundary. Registers x16-x31 do not participate in the calling convention, so
there are only six argument registers, a0-a5, only two callee-saved registers,
s0-s1, and only three temporaries, t0-t2.

NOTE: As a consequence, stack alignment is 32-bit when passing arguments by stack
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This is more than just non-normative text, this is an actual specification change (to match what GCC apparently does) regarding how register pairs are handled

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@pcwang-thead pcwang-thead Mar 28, 2022 •
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I agree with you, but I think we should describe it in more details. And since ILP32E(GCC) has been used by some customers, we should be careful of big changes.

There are some discussions three years ago (riscvarchive/riscv-gcc#148), we may:

  • align stack to 8 bytes.
  • or pass arguments with size of 2*XLEN differently and write it in specification document.

I am looking forward to your advice.

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I would prefer to make a ABI fix on GCC, and add one more rule for require 16 byte stack alignment, but I expect that will happen after psABI 1.0 release.

That would be a ABI incomparable change, but we already put a disclaimer there to notice that's unstable...:P

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May I ask why we need 16 bytes stack alignment? would 8 bytes be better if we need to make it an exception?

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@kito-cheng kito-cheng Mar 28, 2022 •
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16 byte since the spec allow RV32EQ as valid combination, but I guess I should spend more time to make sure 2*XLEN is enough or we should require 16 byte to make sure RV32EQ is also valid.

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Thanks! I will follow up your fantastic works.

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That should be 2 * XLEN is enough since more than that will passed in stack.

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That makes sense to me.

and variadic arguments with 2×XLEN-bit alignment and size at most 2×XLEN bits are
not passed in an aligned register pair.

If used with an ISA that has any of the registers x16-x31 and f0-f31, then
these registers are considered temporaries.

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