Merge pull request #1 from ved-rivos/initial

initial version

Makefile

@@ -13,13 +13,13 @@
 # the Doc Template for RISC-V Extensions.
 
 DATE ?= $(shell date +%Y-%m-%d)
-VERSION ?= v0.0.0
-REVMARK ?= Draft
+VERSION ?= v0.7.0
+REVMARK ?= Development
 DOCKER_RUN := docker run --rm -v ${PWD}:/build -w /build \
 riscvintl/riscv-docs-base-container-image:latest
 
-HEADER_SOURCE := header.adoc
-PDF_RESULT := spec-sample.pdf
+HEADER_SOURCE := b.adoc
+PDF_RESULT := riscv-b.pdf
 
 ASCIIDOCTOR_PDF := asciidoctor-pdf
 OPTIONS := --trace \
@@ -29,10 +29,9 @@ OPTIONS := --trace \
            -a revremark=${REVMARK} \
            -a revdate=${DATE} \
            -a pdf-fontsdir=docs-resources/fonts \
-           -a pdf-theme=docs-resources/themes/riscv-pdf.yml \
+           -a pdf-style=docs-resources/themes/riscv-pdf.yml \
            --failure-level=ERROR
-REQUIRES := --require=asciidoctor-bibtex \
-            --require=asciidoctor-diagram \
+REQUIRES := --require=asciidoctor-diagram \
             --require=asciidoctor-mathematical
 
 .PHONY: all build clean build-container build-no-container
@@ -41,7 +40,7 @@ all: build
 
 build: 
 	@echo "Checking if Docker is available..."
-	@if command -v docker >/dev/null 2>&1 ; then \
+	@if command -v docker &> /dev/null ; then \
 		echo "Docker is available, building inside Docker container..."; \
 		$(MAKE) build-container; \
 	else \

b.adoc

@@ -0,0 +1,71 @@
+[[header]]
+:description: B Standard Extension for Bit Manipulation Instructions
+:company: RISC-V.org
+:revdate: 12/2023
+:revnumber: 0.7
+:revremark: This document is in development state. See http://riscv.org/spec-state for details.
+:url-riscv: http://riscv.org
+:doctype: book
+:preface-title: Preamble
+:colophon:
+:appendix-caption: Appendix
+:imagesdir: images
+:title-logo-image: image:risc-v_logo.png[pdfwidth=3.25in,align=center]
+// Settings:
+:experimental:
+:reproducible:
+// needs to be changed? bug discussion started
+//:WaveDromEditorApp: app/wavedrom-editor.app
+:imagesoutdir: images
+:icons: font
+:lang: en
+:listing-caption: Listing
+:sectnums:
+:toc: left
+:toclevels: 4
+:source-highlighter: pygments
+ifdef::backend-pdf[]
+:source-highlighter: coderay
+endif::[]
+:data-uri:
+:hide-uri-scheme:
+:stem: latexmath
+:footnote:
+:xrefstyle: short
+
+= B Standard Extension for Bit Manipulation Instructions
+
+// Preamble
+[WARNING]
+.This document is in the link:http://riscv.org/spec-state[Development state]
+====
+Assume everything can change. This draft specification will change before being
+accepted as standard, so implementations made to this draft specification will
+likely not conform to the future standard.
+====
+
+[preface]
+=== Copyright and license information
+This specification is licensed under the Creative Commons
+Attribution 4.0 International License (CC-BY 4.0). The full
+license text is available at
+https://creativecommons.org/licenses/by/4.0/.
+
+Copyright 2023 by RISC-V International.
+
+[preface]
+=== Contributors
+This RISC-V specification has been contributed to directly or indirectly by:
+Ved Shanbhogue
+
+== B Standard Extension for Bit Manipulation Instructions
+
+The B standard extension includes instructions provided by the Zba, Zbb,
+and Zbs extensions.
+
+=== Privileged Architecture Implications
+
+Bit 1 of the `misa` register encodes the presence of the B standard extension.
+When `misa.B` is 1, the implementation supports the instructions provided by the
+Zba, Zbb, and Zbs extensions. When `misa.B` is 0, it indicates that at least one
+of the Zba, Zbb, or Zbs extensions is not supported.