Flatten changelog as v1.13 (#1424)

* Flatten changelog as v1.13

Integrated changelog for 1.13 with last document version changes which consisted of
integration of ratified specs.

* Fix a table.

Table row wasn't spanning enough columns.

* strip third digit from priv version numbers

* fix version number of supervisor ISA

* bump priv version to 20240528

* reorganize priv preface

---------

Co-authored-by: Andrew Waterman <[email protected]>

src/indirect-csr.adoc

@@ -1,5 +1,5 @@
 [[indirect-csr]]
-== "Smcsrind/Sscsrind" Indirect CSR Access, Version 1.0.0
+== "Smcsrind/Sscsrind" Indirect CSR Access, Version 1.0
 
 [[intro]]
 === Introduction
@@ -331,4 +331,4 @@ incorporates the bit defined above for `hstateen0` but not that for
 [NOTE]
 ====
 CSR address space is reserved for a possible future "Sucsrind" extension that extends indirect CSR access to user mode.
-====
+====

src/priv-preface.adoc

@@ -1,10 +1,10 @@
 [colophon]
 = Preface
 
-[.big]*_Preface to Version 20240326_*
+[.big]*_Preface to Version 20240528_*
 
 This document describes the RISC-V privileged architecture. This
-release, version 20240213, contains the following versions of the RISC-V ISA
+release, version 20240528, contains the following versions of the RISC-V ISA
 modules:
 
 [%autowidth,float="center",align="center",cols="^,<,^",options="header",]
@@ -28,14 +28,14 @@ _Supervisor ISA_ +
 *Hypervisor ISA*  
 
 |_1.13_ +
-*1.0.0* +
-*1.0.0* +
-*1.0.0* +
-*1.0.0* +
-*1.0.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
 _1.13_ +
-*1.0.0* +
-_0.1_ +
+*1.0* +
 *1.0* +
 *1.0* +
 *1.0* +
@@ -50,7 +50,6 @@ _0.1_ +
 *Ratified* +
 *Ratified* +
 *Ratified* +
-_Draft_ +
 *Ratified* +
 _Draft_ +
 *Ratified* +
@@ -59,63 +58,20 @@ _Draft_ +
 *Ratified* +
 *Ratified* +
 *Ratified* +
-*Ratified*
-|===
-
-The changes in this version of the document include:
-
-* The inclusion of all ratified extensions through March 2024.
-* The concept of vacant memory regions has been superseded by inaccessible memory or I/O regions.
-
-[.big]*_Preface to Version 20240213_*
-
-This document describes the RISC-V privileged architecture. This
-release, version 20240213, contains the following versions of the RISC-V ISA
-modules:
-
-[%autowidth,float="center",align="center",cols="^,<,^",options="header",]
-|===
-|Module |Version |Status
-|_Machine ISA_ +
-_Supervisor ISA_ +
-_Smrnmi Extension_ +
-*Svade Extension* +
-*Svnapot Extension* + 
-*Svpbmt Extension* +  
-*Svinval Extension* + 
-*Svadu Extension* +
-*Hypervisor ISA*    
-|_1.13_ +
-_1.13_ +
-_0.1_ +
-*1.0* +
-*1.0* +
-*1.0* +
-*1.0* +
-*1.0* +
-*1.0* 
-|_Draft_ +
-_Draft_ +
-_Draft_ +
-*Ratified* +
-*Ratified* +
-*Ratified* +
-*Ratified* +
 *Ratified* +
 *Ratified*
 |===
 
-The following changes have been made since version 1.12, which, while
-not strictly backwards compatible, are not anticipated to cause software
-portability problems in practice:
+The following changes have been made since version 1.12 of the Machine and
+Supervisor ISAs, which, while not strictly backwards compatible, are not
+anticipated to cause software portability problems in practice:
 
 * Redefined `misa`.MXL to be read-only, making MXLEN a constant.
 * Added the constraint that SXLEN&#8805;UXLEN.
 
-Additionally, the following compatible changes have been made to the Machine ISA since
-version 1.12:
+Additionally, the following compatible changes have been
+made to the Machine and Supervisor ISAs since version 1.12:
 
-* Transliterated the document from LaTeX into AsciiDoc.
 * Defined the `misa`.V field to reflect that the V extension has been
 implemented.
 * Defined the RV32-only `medelegh` and `hedelegh` CSRs.
@@ -125,7 +81,13 @@ implemented.
 * Defined hardware error and software check exception codes.
 * Specified synchronization requirements when changing the PBMTE fields
 in `menvcfg` and `henvcfg`.
-* Incorporated Svade and Svadu extension specifications.
+* Exposed count-overflow interrups to VS-mode.
+
+Finally, the following clarifications and document improvments have been made
+since the last document release:
+
+* Transliterated the document from LaTeX into AsciiDoc.
+* Included all ratified extensions through March 2024.
 * Clarified that "platform- or custom-use" interrupts are actually
 "platform-use interrupts", where the platform can choose to make some custom.
 * Clarified semantics of explicit accesses to CSRs wider than XLEN bits.
@@ -138,7 +100,7 @@ in `menvcfg` and `henvcfg`.
 be set to a nonzero value but sometimes not.
 * Clarified exception behavior of unimplemented or inaccessible CSRs.
 * Clarified that Svpbmt allows implementations to override additional PMAs.
-* Exposed count-overflow interrups to VS-mode.
+* Replaced the concept of vacant memory regions with inaccessible memory or I/O regions.
 
 [.big]*_Preface to Version 20211203_*
 

src/riscv-privileged.adoc

@@ -2,7 +2,7 @@
 = The RISC-V Instruction Set Manual: Volume II: Privileged Architecture
 :description: Volume II - Privileged Architecture
 :company: RISC-V.org
-:revnumber: 20240411
+:revnumber: 20240528
 //:revremark: Pre-release version
 //development: assume everything can change
 //stable: assume everything could change

src/rvwmo.adoc

@@ -515,7 +515,7 @@ register(s) to destination register(s) as specified
 
 |CSRRCI ‡ |_csr_ |_rd_, _csr_^*^  | |^*^unless uimm[4:0]=0
 
-4+| ‡ carries a dependency from _csr_ to _rd_
+5+| ‡ carries a dependency from _csr_ to _rd_
 |===
 
 .RV64I Base Integer Instruction Set

src/smcdeleg.adoc

@@ -1,5 +1,5 @@
 [[smcdeleg]]
-== "Smcdeleg" Counter Delegation Extension, Version 1.0.0
+== "Smcdeleg" Counter Delegation Extension, Version 1.0
 
 In modern “Rich OS” environments, hardware performance monitoring
 resources are managed by the kernel, kernel driver, and/or hypervisor.

src/smcntrpmf.adoc

@@ -1,5 +1,5 @@
 [[smcntrpmf]]
-== "Smcntrpmf" Cycle and Instret Privilege Mode Filtering, Version 1.0.0
+== "Smcntrpmf" Cycle and Instret Privilege Mode Filtering, Version 1.0
 
 [[intro]]
 === Introduction

src/smepmp.adoc

@@ -1,5 +1,5 @@
 [[smepmp]]
-== "Smepmp" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0.0
+== "Smepmp" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0
 === Introduction
 
 Being able to access the memory of a process running at a high privileged execution mode, such as the Supervisor or Machine mode, from a lower privileged mode such as the User mode, introduces an obvious attack vector since it allows for an attacker to perform privilege escalation, and tamper with the code and/or data of that process. A less obvious attack vector exists when the reverse happens, in which case an attacker instead of tampering with code and/or data that belong to a high-privileged process, can tamper with the memory of an unprivileged / less-privileged process and trick the high-privileged process to use or execute it.

src/smstateen.adoc

@@ -1,5 +1,5 @@
 [[smstateen]]
-== "Smstateen/Ssstateen" Extensions, Version 1.0.0
+== "Smstateen/Ssstateen" Extensions, Version 1.0
 
 The implementation of optional RISC-V extensions has the potential to open
 covert channels between separate user threads, or between separate guest OSes

src/sscofpmf.adoc

@@ -1,5 +1,5 @@
 [[Sscofpmf]]
-== "Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0.0
+== "Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0
 
 The current Privileged specification defines mhpmevent CSRs to select and
 control event counting by the associated hpmcounter CSRs, but provides no

src/sstc.adoc

@@ -1,5 +1,5 @@
 [[Sstc]]
-== "Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0.0
+== "Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0
 
 The current Privileged arch specification only defines a hardware mechanism for
 generating machine-mode timer interrupts (based on the mtime and mtimecmp