Fixing formatting

Fixing the monospaced formatting on some text.

src/sscofpmt.adoc

@@ -33,9 +33,7 @@ interrupt that is assigned to bit 13 in the mip/mie/sip/sie registers.
 This extension expands the hardware performance monitor description and extends
 the mhpmevent registers to 64 bits (in RV32) as follows:
 
-The hardware performance monitor includes 29 additional 64-bit event counters
-and 29 associated 64-bit event selector registers - the
-mhpmcounter3–mhpmcounter31 and mhpmevent3–mhpmevent31 CSRs.
+The hardware performance monitor includes 29 additional 64-bit event counters and 29 associated 64-bit event selector registers - the mhpmcounter3–mhpmcounter31 and mhpmevent3–mhpmevent31 CSRs.
 
 The mhpmcounters are WARL registers that support up to 64 bits of precision on
 RV32 and RV64.
@@ -72,8 +70,8 @@ bit [57] 0 - Reserved for possible future modes
 
 bit [56] 0 - Reserved for possible future modes
 
-Each of the five `x`INH bits, when set, inhibit counting of events while in
-privilege mode `x`. All-zeroes for these bits results in counting of events in
+Each of the five ``x``INH bits, when set, inhibit counting of events while in
+privilege mode ``x``. All-zeroes for these bits results in counting of events in
 all modes.
 
 The OF bit is set when the corresponding hpmcounter overflows, and remains set