Relax Svpbmt sequence slightly

CBOs will ignore Svpbmt, and so either a cacheable or uncacheable
address suffices.

src/supervisor.tex

@@ -2479,10 +2479,8 @@ \chapter{``Svpbmt'' Standard Extension for Page-Based Memory Types, Version 1.0}
 of coherence.
 Executing the following sequence between such accesses prevents both loss of
 coherence and loss of memory ordering:
-{\tt fence iorw, iorw}, followed by {\tt cbo.flush} to a cacheable address of
+{\tt fence iorw, iorw}, followed by {\tt cbo.flush} to an address of
 that location, followed by a {\tt fence iorw, iorw}.
-Note, it is {\em not} sufficient for the {\tt cbo.flush} to target
-a non-cacheable address of that location.
 
 \begin{commentary}
 It follows that, if the same location might later be referenced using the