zvkned: add vaesz.vs

The "vaesz.vs" instruction performs a round zero
encryption/decryption

This instruction is only available in ".vs" form.
The new round state output of each element group is produced
by XORing the round key "vs2" with each element group of "vd".

Signed-off-by: Charalampos Mitrodimas <[email protected]>

model/riscv_insts_zvkned.sail

@@ -378,3 +378,51 @@ function clause execute (RISCV_VAESKF2_VI(vs2, rnd, vd)) = {
     RETIRE_SUCCESS
   }
 }
+
+/* VAESZ.VS */
+
+union clause ast = RISCV_VAESZ_VS : (regidx, regidx)
+
+mapping clause encdec = RISCV_VAESZ_VS(vs2, vd)		if (haveRVV() & haveZvkned())
+ <-> 0b1010011 @ vs2 @ 0b00111 @ 0b010 @ vd @ 0b1110111 if (haveRVV() & haveZvkned())
+
+mapping clause assembly = RISCV_VAESZ_VS(vs2, vd)
+ <-> "vaesz.vs" ^ sep() ^ vreg_name(vd)
+     		^ sep() ^ vreg_name(vs2)
+
+function clause execute (RISCV_VAESZ_VS(vs2, vd)) = {
+  let SEW      = get_sew();
+  let LMUL_pow = get_lmul_pow();
+  let LMUL     = if LMUL_pow < 0 then 0 else LMUL_pow;
+  let VLEN     = int_power(2, get_vlen_pow());
+  let num_elem = get_num_elem(LMUL_pow, SEW);
+
+  if (zvk_check_elements(VLEN, num_elem, LMUL, SEW) == false)
+  then {
+    handle_illegal();
+    RETIRE_FAIL
+  } else {
+    let 'n = num_elem;
+    let 'm = SEW;
+    assert('m == 32);
+    let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
+    let vd_val  : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);
+    result      : vector('n, dec, bits('m)) = undefined;
+    mask        : vector('n, dec, bool)     = undefined;
+
+    w : vector(4, dec, bits(32)) = undefined;
+
+    foreach (i from 0 to (num_elem - 1)) {
+      assert(0 <= i & i < 'n);
+      let vd_state : bits(128) = to_bits(128, signed(vd_val[i]));
+      let vs2_key  : bits(128) = to_bits(128, signed(vs2_val[i]));
+      let ark      : bits(128) = vd_state ^ vs2_key;
+
+      result[i] = ark[31..0];
+    };
+
+    write_single_vreg(num_elem, 'm, vd, result);
+    vstart = EXTZ(0b0);
+    RETIRE_SUCCESS
+  }
+}