Middle of work _6_

robehn · Jan 13, 2025 · 1ba5311 · 1ba5311
1 parent 13227fe
commit 1ba5311
Showing 1 changed file with 33 additions and 26 deletions.
diff --git a/src/hotspot/cpu/riscv/assembler_riscv.hpp b/src/hotspot/cpu/riscv/assembler_riscv.hpp
@@ -937,6 +937,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
     fp_base(Rd->raw_encoding(), Rs1->raw_encoding(), Rs2, rm, fmt, funct5);
   }
 
+  void fp_base(Register Rd, FloatRegister Rs1, int Rs2, int rm, int fmt, int funct5) {
+    fp_base(Rd->raw_encoding(), Rs1->raw_encoding(), Rs2, (RoundingMode)rm, fmt, funct5);
+  }
+
   void fp_base(FloatRegister Rd, Register Rs1, int Rs2, RoundingMode rm, int fmt, int funct5) {
     fp_base(Rd->raw_encoding(), Rs1->raw_encoding(), Rs2, rm, fmt, funct5);
   }
@@ -1153,13 +1157,39 @@ enum operand_size { int8, int16, int32, uint32, int64 };
   }
 
   void fmv_h_x(FloatRegister Rd, Register Rs1) {
-    fp_base(Rd, Rs1, 0b00000, 0b00, 0b10, 0b11110);
+    fp_base(Rd, Rs1, 0b00000, 0b000, 0b10, 0b11110);
   }
+
   void fmv_w_x(FloatRegister Rd, Register Rs1) {
-    fp_base(Rd, Rs1, 0b00000, 0b00, 0b00, 0b11110);
+    fp_base(Rd, Rs1, 0b00000, 0b000, 0b00, 0b11110);
   }
+
   void fmv_d_x(FloatRegister Rd, Register Rs1) {
-    fp_base(Rd, Rs1, 0b00000, 0b00, 0b01, 0b11110);
+    fp_base(Rd, Rs1, 0b00000, 0b000, 0b01, 0b11110);
+  }
+
+  void fclass_s(Register Rd, FloatRegister Rs1) {
+    fp_base(Rd, Rs1, 0b00000, 0b001, 0b00, 0b11110);
+  }
+
+  void fclass_d(Register Rd, FloatRegister Rs1) {
+    fp_base(Rd, Rs1, 0b00000, 0b001, 0b01, 0b11110);
+  }
+
+  void fmv_x_w(Register Rd, FloatRegister Rs1) {
+    fp_base(Rd, Rs1, 0b00000, 0b000, 0b00, 0b11110);
+  }
+
+  void fmv_x_d(Register Rd, FloatRegister Rs1) {
+    fp_base(Rd, Rs1, 0b00000, 0b000, 0b01, 0b11110);
+  }
+
+  void fclass_h(Register Rd, FloatRegister Rs1) {
+    fp_base(Rd, Rs1, 0b00000, 0b001, 0b10, 0b11110);
+  }
+
+  void fmv_x_h(Register Rd, FloatRegister Rs1) {
+    fp_base(Rd, Rs1, 0b00000, 0b000, 0b10, 0b11110);
   }
 
  private:
@@ -1230,29 +1260,6 @@ enum operand_size { int8, int16, int32, uint32, int64 };
     fp_fm<0b1001111,  0b01>(Rd, Rs1, Rs2, Rs3, rm);
   }
 
-
-// Float and Double Conversion/Classify Instruction
-#define INSN(NAME, op, funct3, funct5, funct7)            \
-  void NAME(Register Rd, FloatRegister Rs1) {             \
-    unsigned insn = 0;                                    \
-    patch((address)&insn, 6, 0, op);                      \
-    patch_reg((address)&insn, 7, Rd);                     \
-    patch((address)&insn, 14, 12, funct3);                \
-    patch_reg((address)&insn, 15, Rs1);                   \
-    patch((address)&insn, 20, funct5);                    \
-    patch((address)&insn, 31, 25, funct7);                \
-    emit(insn);                                           \
-  }
-
-  INSN(fclass_s, OP_FP_MAJOR, 0b001, 0b00000, 0b1110000);
-  INSN(fclass_d, OP_FP_MAJOR, 0b001, 0b00000, 0b1110001);
-  INSN(fmv_x_w,  OP_FP_MAJOR, 0b000, 0b00000, 0b1110000);
-  INSN(fmv_x_d,  OP_FP_MAJOR, 0b000, 0b00000, 0b1110001);
-
-  INSN(fclass_h, OP_FP_MAJOR, 0b001, 0b00000, 0b1110010);
-  INSN(fmv_x_h,  OP_FP_MAJOR, 0b000, 0b00000, 0b1110010);
-#undef INSN
-
 // ==========================
 // RISC-V Vector Extension
 // ==========================