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@robehn
robehn committed Nov 16, 2023
1 parent a579635 commit 2ebb3aa
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Showing 3 changed files with 99 additions and 73 deletions.
67 changes: 63 additions & 4 deletions src/hotspot/cpu/riscv/assembler_riscv.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1867,9 +1867,9 @@ enum Nf {
}

INSN(rev8, 0b0010011, 0b101, 0b011010111000);
INSN(sext_b, 0b0010011, 0b001, 0b011000000100);
INSN(sext_h, 0b0010011, 0b001, 0b011000000101);
INSN(zext_h, 0b0111011, 0b100, 0b000010000000);
INSN(_sext_b, 0b0010011, 0b001, 0b011000000100);
INSN(_sext_h, 0b0010011, 0b001, 0b011000000101);
INSN(_zext_h, 0b0111011, 0b100, 0b000010000000);
INSN(clz, 0b0010011, 0b001, 0b011000000000);
INSN(clzw, 0b0011011, 0b001, 0b011000000000);
INSN(ctz, 0b0010011, 0b001, 0b011000000001);
Expand Down Expand Up @@ -2960,6 +2960,33 @@ enum Nf {
}
}

void sext_h_cmux(Register Rd_Rs2, Register Rs1) {
assert(UseZbb, "must be");
if (do_compress_zcb(Rd_Rs2) && (Rd_Rs2 == Rs1)) {
c_sext_h(Rd_Rs2);
return;
}
_sext_h(Rd_Rs2, Rs1);
}

void sext_b_cmux(Register Rd_Rs2, Register Rs1) {
assert(UseZbb, "must be");
if (do_compress_zcb(Rd_Rs2) && (Rd_Rs2 == Rs1)) {
c_sext_b(Rd_Rs2);
return;
}
_sext_b(Rd_Rs2, Rs1);
}

void zext_h_cmux(Register Rd_Rs2, Register Rs1) {
assert(UseZbb, "must be");
if (do_compress_zcb(Rd_Rs2) && (Rd_Rs2 == Rs1)) {
c_zext_h(Rd_Rs2);
return;
}
_zext_h(Rd_Rs2, Rs1);
}

// Format CU, c.[sz]ext.*, c.no
template <uint8_t InstructionType>
void c_u_imp(Register Rs1) {
Expand All @@ -2975,11 +3002,15 @@ enum Nf {

public:

// Prerequisites: Zcb
void c_lh(Register Rd_Rs2, Register Rs1, const int32_t uimm) { c_lh_imp<false>(Rd_Rs2, Rs1, uimm); }
void c_lhu(Register Rd_Rs2, Register Rs1, const int32_t uimm) { c_lh_imp<true >(Rd_Rs2, Rs1, uimm); }
void lh(Register Rd_Rs2, Register Rs1, const int32_t uimm) { lh_cmux_imp<false>(Rd_Rs2, Rs1, uimm); }

// Prerequisites: Zcb
void c_lhu(Register Rd_Rs2, Register Rs1, const int32_t uimm) { c_lh_imp<true >(Rd_Rs2, Rs1, uimm); }
void lhu(Register Rd_Rs2, Register Rs1, const int32_t uimm) { lh_cmux_imp<true >(Rd_Rs2, Rs1, uimm); }

// Prerequisites: Zcb
// Format CLB, single instruction
void c_lbu(Register Rd_Rs2, Register Rs1, uint32_t uimm) {
assert_cond(uimm <= 3);
Expand All @@ -3002,6 +3033,7 @@ enum Nf {
}
}

// Prerequisites: Zcb
// Format CSB, single instruction
void c_sb(Register Rd_Rs2, Register Rs1, uint32_t uimm) {
assert_cond(uimm <= 3);
Expand All @@ -3024,6 +3056,7 @@ enum Nf {
}
}

// Prerequisites: Zcb
// Format CSH, single instruction
void c_sh(Register Rd_Rs2, Register Rs1, uint32_t uimm) {
assert_cond(uimm == 0 || uimm == 2);
Expand All @@ -3046,30 +3079,56 @@ enum Nf {
}
}

// Prerequisites: Zcb
// Format CS
void c_zext_b(Register Rs1) {
c_u_imp<0b000>(Rs1);
}

void sext_b(Register Rd_Rs2, Register Rs1) {
sext_b_cmux(Rd_Rs2, Rs1);
}

// Prerequisites: Zcb, Zbb
// Format CS
void c_sext_b(Register Rs1) {
c_u_imp<0b001>(Rs1);
}

void zext_h(Register Rd_Rs2, Register Rs1) {
zext_h_cmux(Rd_Rs2, Rs1);
}

// Prerequisites: Zcb, Zbb
// Format CS
void c_zext_h(Register Rs1) {
c_u_imp<0b010>(Rs1);
}

void sext_h(Register Rd_Rs2, Register Rs1) {
sext_h_cmux(Rd_Rs2, Rs1);
}

// Prerequisites: Zcb, Zbb
// Format CS
void c_sext_h(Register Rs1) {
c_u_imp<0b011>(Rs1);
}

// Prerequisites: Zcb, Zba
// Format CS
void c_zext_w(Register Rs1) {
c_u_imp<0b100>(Rs1);
}

// Prerequisites: Zcb
// Format CS
void c_not(Register Rs1) {
c_u_imp<0b101>(Rs1);
}

// Prerequisites: Zcb (M or Zmmul)
// Format CS
void c_mul(Register Rd_Rs1, Register Rs2) {
// Format CA, c.mul and others
uint16_t insn = 0;
Expand Down
97 changes: 28 additions & 69 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4385,92 +4385,51 @@ void MacroAssembler::shadd(Register Rd, Register Rs1, Register Rs2, Register tmp
}

void MacroAssembler::zero_extend(Register dst, Register src, int bits) {
// TODO refactor masm + asm
// This code is not nice, we can do much better if refactored.
if (bits == 32) {
if (UseZba) {
zext_w(dst, src);
return;
}
}
if (bits == 16) {
if (do_compress_zcb(dst)) {
if (dst == src) {
c_zext_h(src);
return ;
}
if (!UseZbb && dst != x0) {
c_mv(dst, src);
c_zext_h(dst);
switch (bits) {
case 32:
if (UseZba) {
zext_w(dst, src);
return;
}
}
if (UseZbb) {
zext_h(dst, src);
return;
}
}
if (bits == 8) {
if (do_compress_zcb(dst)) {
if (dst == src) {
c_zext_b(src);
break;
case 16:
if (UseZbb) {
zext_h(dst, src);
return;
}
if (!UseZbb && dst != x0) {
c_mv(dst, src);
c_zext_b(dst);
break;
case 8:
if (UseZbb) {
zext_b(dst, src);
return;
}
}
if (UseZbb) {
zext_b(dst, src);
return;
}
break;
default:
break;
}
slli(dst, src, XLEN - bits);
srli(dst, dst, XLEN - bits);
}

void MacroAssembler::sign_extend(Register dst, Register src, int bits) {
// TODO refactor masm + asm
// This code is not nice, we can do much better if refactored.
if (bits == 32) {
sext_w(dst, src);
return;
}
if (bits == 16) {
if (do_compress_zcb(dst)) {
if (dst == src) {
c_sext_h(src);
return ;
}
if (!UseZbb && dst != x0) {
c_mv(dst, src);
c_sext_h(dst);
return;
}
}
if (UseZbb) {
sext_h(dst, src);
switch (bits) {
case 32:
sext_w(dst, src);
return;
}
}
if (bits == 8) {
if (do_compress_zcb(dst)) {
if (dst == src) {
c_sext_b(src);
case 16:
if (UseZbb) {
sext_h(dst, src);
return;
}
if (!UseZbb && dst != x0) {
c_mv(dst, src);
c_sext_b(dst);
break;
case 8:
if (UseZbb) {
sext_b(dst, src);
return;
}
}
if (UseZbb) {
sext_b(dst, src);
return;
}
break;
default:
break;
}
slli(dst, src, XLEN - bits);
srai(dst, dst, XLEN - bits);
Expand Down
8 changes: 8 additions & 0 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -484,6 +484,10 @@ class MacroAssembler: public Assembler {
}

inline void zext_b(Register Rd, Register Rs) {
if (UseZbb && do_compress_zcb(Rd) && (Rd == Rs)) {
c_zext_b(Rd);
return;
}
andi(Rd, Rs, 0xFF);
}

Expand All @@ -506,6 +510,10 @@ class MacroAssembler: public Assembler {
// Bit-manipulation extension pseudo instructions
// zero extend word
inline void zext_w(Register Rd, Register Rs) {
assert(UseZba, "must be");
if (do_compress_zcb(Rd) && (Rd == Rs)) {
c_zext_w(Rd);
}
add_uw(Rd, Rs, zr);
}

Expand Down

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