tier1

robehn · Nov 15, 2023 · 9474b77 · 9474b77
1 parent 18e6ee6
commit 9474b77
Showing 1 changed file with 0 additions and 2 deletions.
diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
@@ -4387,7 +4387,6 @@ void MacroAssembler::shadd(Register Rd, Register Rs1, Register Rs2, Register tmp
 void MacroAssembler::zero_extend(Register dst, Register src, int bits) {
   // TODO refactor masm + asm
   // This code is not nice, we can do much better if refactored.
-  assert(bits == 8 || bits == 16 || bits == 32, "must be");
   if (bits == 32) {
     if (UseZba) {
       zext_w(dst, src);
@@ -4435,7 +4434,6 @@ void MacroAssembler::zero_extend(Register dst, Register src, int bits) {
 void MacroAssembler::sign_extend(Register dst, Register src, int bits) {
   // TODO refactor masm + asm
   // This code is not nice, we can do much better if refactored.
-  assert(bits == 8 || bits == 16 || bits == 32, "must be");
   if (bits == 32) {
     sext_w(dst, src);
     return;