temp

robehn · Mar 8, 2024 · d6e69c2 · d6e69c2
1 parent 51a5ac9
commit d6e69c2
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
@@ -3148,7 +3148,6 @@ void MacroAssembler::atomic_cas(
 }
 
 void MacroAssembler::far_jump(const Address &entry, Register tmp) {
-  assert(ReservedCodeCacheSize < 4*G, "branch out of range");
   assert(CodeCache::find_blob(entry.target()) != nullptr,
          "destination of far call not found in code cache");
   assert(entry.rspec().type() == relocInfo::external_word_type
@@ -3163,7 +3162,6 @@ void MacroAssembler::far_jump(const Address &entry, Register tmp) {
 }
 
 void MacroAssembler::far_call(const Address &entry, Register tmp) {
-  assert(ReservedCodeCacheSize < 4*G, "branch out of range");
   assert(CodeCache::find_blob(entry.target()) != nullptr,
          "destination of far call not found in code cache");
   assert(entry.rspec().type() == relocInfo::external_word_type

diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
@@ -610,7 +610,9 @@ class MacroAssembler: public Assembler {
     assert_cond(dest != nullptr);
     assert(temp != noreg, "expecting a register");
     int32_t offset = 0;
-    la(temp, dest, offset);
+    // la(temp, dest, offset);
+    bool mustbe = la_relative(temp, dest, offset);
+    assert(mustbe, "Must be");
     jalr(x1, temp, offset);
   }