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robehn · Nov 15, 2023 · e71f0be · e71f0be
1 parent 4979458
commit e71f0be
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Showing 2 changed files with 17 additions and 15 deletions.
diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
@@ -4389,11 +4389,13 @@ void MacroAssembler::zero_extend(Register dst, Register src, int bits) {
   // This code is not nice, we can do much better if refactored.
   assert(bits == 8 || bits == 16 || bits == 32, "must be");
   if (bits == 32) {
-    zext_w(dst, src);
-    return;
+    if (UseZba) {
+      zext_w(dst, src);
+      return;
+    }
   }
   if (bits == 16) {
-    if (do_compress_zcb()) {
+    if (do_compress_zcb(dst)) {
       if (dst == src) {
         c_zext_h(src);
         return ;
@@ -4403,13 +4405,14 @@ void MacroAssembler::zero_extend(Register dst, Register src, int bits) {
         c_zext_h(dst);
         return;
       }
-    } else if (UseZbb) {
+    }
+    if (UseZbb) {
       zext_h(dst, src);
       return;
     }
   }
   if (bits == 8) {
-    if (do_compress_zcb()) {
+    if (do_compress_zcb(dst)) {
       if (dst == src) {
         c_zext_b(src);
         return;
@@ -4419,15 +4422,12 @@ void MacroAssembler::zero_extend(Register dst, Register src, int bits) {
         c_zext_b(dst);
         return;
       }
-    } else if (UseZbb) {
+    }
+    if (UseZbb) {
       zext_b(dst, src);
       return;
     }
   }
-  if (UseZba && bits == 32) {
-    zext_w(dst, src);
-    return;
-  }
 
   slli(dst, src, XLEN - bits);
   srli(dst, dst, XLEN - bits);
@@ -4442,7 +4442,7 @@ void MacroAssembler::sign_extend(Register dst, Register src, int bits) {
     return;
   }
   if (bits == 16) {
-    if (do_compress_zcb()) {
+    if (do_compress_zcb(dst)) {
       if (dst == src) {
         c_sext_h(src);
         return ;
@@ -4452,13 +4452,14 @@ void MacroAssembler::sign_extend(Register dst, Register src, int bits) {
         c_sext_h(dst);
         return;
       }
-    } else if (UseZbb) {
+    }
+    if (UseZbb) {
       sext_h(dst, src);
       return;
     }
   }
   if (bits == 8) {
-    if (do_compress_zcb()) {
+    if (do_compress_zcb(dst)) {
       if (dst == src) {
         c_sext_b(src);
         return;
@@ -4468,7 +4469,8 @@ void MacroAssembler::sign_extend(Register dst, Register src, int bits) {
         c_sext_b(dst);
         return;
       }
-    } else if (UseZbb) {
+    }
+    if (UseZbb) {
       sext_b(dst, src);
       return;
     }

diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
@@ -464,7 +464,7 @@ class MacroAssembler: public Assembler {
   }
 
   inline void notr(Register Rd, Register Rs) {
-    if (do_compress_zcb() && (Rd == Rs)) {
+    if (do_compress_zcb(Rd) && (Rd == Rs)) {
       c_not(Rd);
     } else {
       xori(Rd, Rs, -1);