azm: Move the AMD64 bits into its own namespace

We'll want to be able to assemble e.g. aarch64 too in the future.
robinlinden · Oct 31, 2023 · 70e4468 · 70e4468
1 parent b738622
commit 70e4468
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Showing 4 changed files with 18 additions and 18 deletions.
diff --git a/azm/BUILD b/azm/BUILD
@@ -3,13 +3,13 @@ load("//bzl:copts.bzl", "HASTUR_COPTS")
 
 cc_library(
     name = "azm",
-    hdrs = ["assembler.h"],
+    hdrs = glob(["**/*.h"]),
     copts = HASTUR_COPTS,
     visibility = ["//visibility:public"],
 )
 
 [cc_test(
-    name = src[:-4],
+    name = src[:-4].replace("/", "_"),
     size = "small",
     srcs = [src],
     copts = HASTUR_COPTS,
@@ -18,7 +18,7 @@ cc_library(
         "//etest",
     ],
 ) for src in glob(
-    include = ["*_test.cpp"],
+    include = ["**/*_test.cpp"],
 )]
 
 cc_binary(

diff --git a/azm/assembler.h → azm/amd64/assembler.h b/azm/assembler.h → azm/amd64/assembler.h
@@ -2,16 +2,16 @@
 //
 // SPDX-License-Identifier: BSD-2-Clause
 
-#ifndef AZM_ASSEMBLER_H_
-#define AZM_ASSEMBLER_H_
+#ifndef AZM_AMD64_ASSEMBLER_H_
+#define AZM_AMD64_ASSEMBLER_H_
 
 #include <cstdint>
 #include <iostream>
 #include <optional>
 #include <utility>
 #include <vector>
 
-namespace azm {
+namespace azm::amd64 {
 
 enum class Reg32 {
     Eax,
@@ -39,7 +39,7 @@ constexpr std::optional<std::uint8_t> register_index(Reg32 reg) {
 }
 
 // https://www.felixcloutier.com/x86/
-class Amd64Assembler {
+class Assembler {
 public:
     [[nodiscard]] std::vector<std::uint8_t> take_assembled() { return std::exchange(assembled_, {}); }
 
@@ -78,6 +78,6 @@ class Amd64Assembler {
     std::vector<std::uint8_t> assembled_;
 };
 
-} // namespace azm
+} // namespace azm::amd64
 
 #endif
diff --git a/azm/assembler_test.cpp → azm/amd64/assembler_test.cpp b/azm/assembler_test.cpp → azm/amd64/assembler_test.cpp
@@ -2,7 +2,7 @@
 //
 // SPDX-License-Identifier: BSD-2-Clause
 
-#include "azm/assembler.h"
+#include "azm/amd64/assembler.h"
 
 #include "etest/etest2.h"
 
@@ -14,7 +14,7 @@ using CodeVec = std::vector<std::uint8_t>;
 
 int main() {
     etest::Suite s{"assembler::amd64"};
-    using namespace azm;
+    using namespace azm::amd64;
 
     s.add_test("Register index", [](etest::IActions &a) {
         a.expect_eq(register_index(Reg32::Eax), 0);
@@ -25,14 +25,14 @@ int main() {
     });
 
     s.add_test("ADD EAX, imm32", [](etest::IActions &a) {
-        Amd64Assembler assembler;
+        Assembler assembler;
 
         assembler.add(Reg32::Eax, Imm32{0x42});
         a.expect_eq(assembler.take_assembled(), CodeVec{0x05, 0x42, 0, 0, 0});
     });
 
     s.add_test("ADD w/ unsupported dst is ud2", [](etest::IActions &a) {
-        Amd64Assembler assembler;
+        Assembler assembler;
 
         assembler.add(Reg32::Edx, Imm32{0x42});
         auto unsupported_add_code = assembler.take_assembled();
@@ -42,7 +42,7 @@ int main() {
     });
 
     s.add_test("MOV r32, imm32", [](etest::IActions &a) {
-        Amd64Assembler assembler;
+        Assembler assembler;
 
         assembler.mov(Reg32::Eax, Imm32{0xdeadbeef});
         a.expect_eq(assembler.take_assembled(), CodeVec{0xb8, 0xef, 0xbe, 0xad, 0xde});
@@ -52,14 +52,14 @@ int main() {
     });
 
     s.add_test("RET", [](etest::IActions &a) {
-        Amd64Assembler assembler;
+        Assembler assembler;
 
         assembler.ret();
         a.expect_eq(assembler.take_assembled(), CodeVec{0xc3});
     });
 
     s.add_test("UD2", [](etest::IActions &a) {
-        Amd64Assembler assembler;
+        Assembler assembler;
 
         assembler.ud2();
         a.expect_eq(assembler.take_assembled(), CodeVec{0x0f, 0x0b});

diff --git a/azm/azm_example.cpp b/azm/azm_example.cpp
@@ -2,15 +2,15 @@
 //
 // SPDX-License-Identifier: BSD-2-Clause
 
-#include "azm/assembler.h"
+#include "azm/amd64/assembler.h"
 
 #include <algorithm>
 #include <iostream>
 #include <iterator>
 
 int main() {
-    using namespace azm;
-    Amd64Assembler assembler;
+    using namespace azm::amd64;
+    Assembler assembler;
     assembler.mov(Reg32::Eax, Imm32{3});
     assembler.add(Reg32::Eax, Imm32{39});
     assembler.mov(Reg32::Ecx, Imm32{0x4321});