Add TDP ram

info.yaml

@@ -17,6 +17,7 @@ project:
   source_files:
     - "project.v"
     - "topEntity.v"
+    - "Clash_TinyTapeout_EthernetMac_TopEntity_topEntity_trueDualPortBlockRamWrapper.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:

src/Clash_TinyTapeout_EthernetMac_TopEntity_topEntity_trueDualPortBlockRamWrapper.v

@@ -0,0 +1,58 @@
+/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.
+** GENERATED BY CLASH 1.6.4. DO NOT MODIFY.
+*/
+`timescale 100fs/100fs
+module Clash_TinyTapeout_EthernetMac_TopEntity_topEntity_trueDualPortBlockRamWrapper
+    ( // Inputs
+      input  clkA // clock
+    , input  enA
+    , input  weA
+    , input [3:0] addrA
+    , input [9:0] datA
+    , input  clkB // clock
+    , input  enB
+    , input  weB
+    , input [3:0] addrB
+    , input [9:0] datB
+
+      // Outputs
+    , output wire [19:0] result
+    );
+
+
+  // trueDualPortBlockRam begin
+  // Shared memory
+  reg [10-1:0] mem [16-1:0];
+
+  reg [9:0] data_slow;
+  reg [9:0] data_fast;
+
+  // Port A
+  always @(posedge clkA) begin
+      if(enA) begin
+          data_slow <= mem[addrA];
+          if(weA) begin
+              data_slow <= datA;
+              mem[addrA] <= datA;
+          end
+      end
+  end
+
+  // Port B
+  always @(posedge clkB) begin
+      if(enB) begin
+          data_fast <= mem[addrB];
+          if(weB) begin
+              data_fast <= datB;
+              mem[addrB] <= datB;
+          end
+      end
+  end
+
+  assign result = {data_slow, data_fast};
+
+  // end trueDualPortBlockRam
+
+
+endmodule
+