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[LLVM][XTHeadVector] update corresponding tests
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@imkiva
imkiva committed Jun 21, 2024
1 parent 1a276de commit 608e6d7
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60 changes: 60 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv0p71/vmand.ll
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Expand Up @@ -4,6 +4,66 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
; RUN: -verify-machineinstrs | FileCheck %s

declare <vscale x 1 x i1> @llvm.riscv.th.vmand.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
iXLen);

define <vscale x 1 x i1> @intrinsic_vmand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1
; CHECK-NEXT: th.vmand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.th.vmand.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
iXLen %2)

ret <vscale x 1 x i1> %a
}

declare <vscale x 2 x i1> @llvm.riscv.th.vmand.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
iXLen);

define <vscale x 2 x i1> @intrinsic_vmand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1
; CHECK-NEXT: th.vmand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.th.vmand.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
iXLen %2)

ret <vscale x 2 x i1> %a
}

declare <vscale x 4 x i1> @llvm.riscv.th.vmand.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
iXLen);

define <vscale x 4 x i1> @intrinsic_vmand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1
; CHECK-NEXT: th.vmand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.th.vmand.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
iXLen %2)

ret <vscale x 4 x i1> %a
}

declare <vscale x 8 x i1> @llvm.riscv.th.vmand.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
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76 changes: 68 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv0p71/vmandn.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -4,13 +4,73 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
; RUN: -verify-machineinstrs | FileCheck %s

declare <vscale x 1 x i1> @llvm.riscv.th.vmandnot.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
iXLen);

define <vscale x 1 x i1> @intrinsic_vmandnot_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.th.vmandnot.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
iXLen %2)

ret <vscale x 1 x i1> %a
}

declare <vscale x 2 x i1> @llvm.riscv.th.vmandnot.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
iXLen);

define <vscale x 2 x i1> @intrinsic_vmandnot_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.th.vmandnot.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
iXLen %2)

ret <vscale x 2 x i1> %a
}

declare <vscale x 4 x i1> @llvm.riscv.th.vmandnot.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
iXLen);

define <vscale x 4 x i1> @intrinsic_vmandnot_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.th.vmandnot.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
iXLen %2)

ret <vscale x 4 x i1> %a
}

declare <vscale x 8 x i1> @llvm.riscv.th.vmandnot.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
iXLen);

define <vscale x 8 x i1> @intrinsic_vmandn_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv8i1:
define <vscale x 8 x i1> @intrinsic_vmandnot_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
Expand All @@ -29,8 +89,8 @@ declare <vscale x 16 x i1> @llvm.riscv.th.vmandnot.nxv16i1(
<vscale x 16 x i1>,
iXLen);

define <vscale x 16 x i1> @intrinsic_vmandn_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv16i1:
define <vscale x 16 x i1> @intrinsic_vmandnot_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
Expand All @@ -49,8 +109,8 @@ declare <vscale x 32 x i1> @llvm.riscv.th.vmandnot.nxv32i1(
<vscale x 32 x i1>,
iXLen);

define <vscale x 32 x i1> @intrinsic_vmandn_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv32i1:
define <vscale x 32 x i1> @intrinsic_vmandnot_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
Expand All @@ -69,8 +129,8 @@ declare <vscale x 64 x i1> @llvm.riscv.th.vmandnot.nxv64i1(
<vscale x 64 x i1>,
iXLen);

define <vscale x 64 x i1> @intrinsic_vmandn_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv64i1:
define <vscale x 64 x i1> @intrinsic_vmandnot_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m8, d1
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
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48 changes: 48 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv0p71/vmclr.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,54 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
; RUN: -verify-machineinstrs | FileCheck %s

declare <vscale x 1 x i1> @llvm.riscv.th.vmclr.nxv1i1(
iXLen);

define <vscale x 1 x i1> @intrinsic_vmclr_m_pseudo_nxv1i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1
; CHECK-NEXT: th.vmclr.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.th.vmclr.nxv1i1(
iXLen %0)

ret <vscale x 1 x i1> %a
}

declare <vscale x 2 x i1> @llvm.riscv.th.vmclr.nxv2i1(
iXLen);

define <vscale x 2 x i1> @intrinsic_vmclr_m_pseudo_nxv2i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1
; CHECK-NEXT: th.vmclr.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.th.vmclr.nxv2i1(
iXLen %0)

ret <vscale x 2 x i1> %a
}

declare <vscale x 4 x i1> @llvm.riscv.th.vmclr.nxv4i1(
iXLen);

define <vscale x 4 x i1> @intrinsic_vmclr_m_pseudo_nxv4i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1
; CHECK-NEXT: th.vmclr.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.th.vmclr.nxv4i1(
iXLen %0)

ret <vscale x 4 x i1> %a
}

declare <vscale x 8 x i1> @llvm.riscv.th.vmclr.nxv8i1(
iXLen);

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60 changes: 60 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv0p71/vmnand.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,66 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
; RUN: -verify-machineinstrs | FileCheck %s

declare <vscale x 1 x i1> @llvm.riscv.th.vmnand.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
iXLen);

define <vscale x 1 x i1> @intrinsic_vmnand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1
; CHECK-NEXT: th.vmnand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.th.vmnand.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
iXLen %2)

ret <vscale x 1 x i1> %a
}

declare <vscale x 2 x i1> @llvm.riscv.th.vmnand.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
iXLen);

define <vscale x 2 x i1> @intrinsic_vmnand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1
; CHECK-NEXT: th.vmnand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.th.vmnand.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
iXLen %2)

ret <vscale x 2 x i1> %a
}

declare <vscale x 4 x i1> @llvm.riscv.th.vmnand.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
iXLen);

define <vscale x 4 x i1> @intrinsic_vmnand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1
; CHECK-NEXT: th.vmnand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.th.vmnand.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
iXLen %2)

ret <vscale x 4 x i1> %a
}

declare <vscale x 8 x i1> @llvm.riscv.th.vmnand.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
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60 changes: 60 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv0p71/vmnor.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,66 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
; RUN: -verify-machineinstrs | FileCheck %s

declare <vscale x 1 x i1> @llvm.riscv.th.vmnor.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
iXLen);

define <vscale x 1 x i1> @intrinsic_vmnor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1
; CHECK-NEXT: th.vmnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.th.vmnor.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
iXLen %2)

ret <vscale x 1 x i1> %a
}

declare <vscale x 2 x i1> @llvm.riscv.th.vmnor.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
iXLen);

define <vscale x 2 x i1> @intrinsic_vmnor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1
; CHECK-NEXT: th.vmnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.th.vmnor.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
iXLen %2)

ret <vscale x 2 x i1> %a
}

declare <vscale x 4 x i1> @llvm.riscv.th.vmnor.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
iXLen);

define <vscale x 4 x i1> @intrinsic_vmnor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1
; CHECK-NEXT: th.vmnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.th.vmnor.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
iXLen %2)

ret <vscale x 4 x i1> %a
}

declare <vscale x 8 x i1> @llvm.riscv.th.vmnor.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
Expand Down
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