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[LLVM][XTHeadVector] Test 16.1 vmclr/vmset
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imkiva committed Apr 10, 2024
1 parent 58985d0 commit a41cbff
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81 changes: 81 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv0p71/vmclr.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \
; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
; RUN: -verify-machineinstrs | FileCheck %s

declare <vscale x 8 x i1> @llvm.riscv.th.vmclr.nxv8i1(
iXLen);

define <vscale x 8 x i1> @intrinsic_vmclr_m_pseudo_nxv8i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1
; CHECK-NEXT: th.vmclr.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.th.vmclr.nxv8i1(
iXLen %0)

ret <vscale x 8 x i1> %a
}

declare <vscale x 16 x i1> @llvm.riscv.th.vmclr.nxv16i1(
iXLen);

define <vscale x 16 x i1> @intrinsic_vmclr_m_pseudo_nxv16i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1
; CHECK-NEXT: th.vmclr.m v0
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: csrr a1, vtype
; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1
; CHECK-NEXT: th.vsetvl zero, a0, a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.th.vmclr.nxv16i1(
iXLen %0)

ret <vscale x 16 x i1> %a
}

declare <vscale x 32 x i1> @llvm.riscv.th.vmclr.nxv32i1(
iXLen);

define <vscale x 32 x i1> @intrinsic_vmclr_m_pseudo_nxv32i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1
; CHECK-NEXT: th.vmclr.m v0
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: csrr a1, vtype
; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1
; CHECK-NEXT: th.vsetvl zero, a0, a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.th.vmclr.nxv32i1(
iXLen %0)

ret <vscale x 32 x i1> %a
}

declare <vscale x 64 x i1> @llvm.riscv.th.vmclr.nxv64i1(
iXLen);

define <vscale x 64 x i1> @intrinsic_vmclr_m_pseudo_nxv64i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m8, d1
; CHECK-NEXT: th.vmclr.m v0
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: csrr a1, vtype
; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1
; CHECK-NEXT: th.vsetvl zero, a0, a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.th.vmclr.nxv64i1(
iXLen %0)

ret <vscale x 64 x i1> %a
}
81 changes: 81 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv0p71/vmset.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \
; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
; RUN: -verify-machineinstrs | FileCheck %s

declare <vscale x 8 x i1> @llvm.riscv.th.vmset.nxv8i1(
iXLen);

define <vscale x 8 x i1> @intrinsic_vmset_m_pseudo_nxv8i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1
; CHECK-NEXT: th.vmset.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.th.vmset.nxv8i1(
iXLen %0)

ret <vscale x 8 x i1> %a
}

declare <vscale x 16 x i1> @llvm.riscv.th.vmset.nxv16i1(
iXLen);

define <vscale x 16 x i1> @intrinsic_vmset_m_pseudo_nxv16i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1
; CHECK-NEXT: th.vmset.m v0
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: csrr a1, vtype
; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1
; CHECK-NEXT: th.vsetvl zero, a0, a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.th.vmset.nxv16i1(
iXLen %0)

ret <vscale x 16 x i1> %a
}

declare <vscale x 32 x i1> @llvm.riscv.th.vmset.nxv32i1(
iXLen);

define <vscale x 32 x i1> @intrinsic_vmset_m_pseudo_nxv32i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1
; CHECK-NEXT: th.vmset.m v0
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: csrr a1, vtype
; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1
; CHECK-NEXT: th.vsetvl zero, a0, a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.th.vmset.nxv32i1(
iXLen %0)

ret <vscale x 32 x i1> %a
}

declare <vscale x 64 x i1> @llvm.riscv.th.vmset.nxv64i1(
iXLen);

define <vscale x 64 x i1> @intrinsic_vmset_m_pseudo_nxv64i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m8, d1
; CHECK-NEXT: th.vmset.m v0
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: csrr a1, vtype
; CHECK-NEXT: th.vsetvli zero, zero, e8, m1, d1
; CHECK-NEXT: th.vsetvl zero, a0, a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.th.vmset.nxv64i1(
iXLen %0)

ret <vscale x 64 x i1> %a
}

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