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[NFC] Reformat clang tests for better automated testing in CI/qemu #107

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May 7, 2024
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[NFC] Reformat clang tests for better automated testing in CI/qemu #107

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65 changes: 33 additions & 32 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/indexed/thead/vloxei16.c
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67 changes: 34 additions & 33 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/indexed/thead/vloxei32.c
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57 changes: 29 additions & 28 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/indexed/thead/vloxei64.c
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51 changes: 26 additions & 25 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/indexed/thead/vloxei8.c
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191 changes: 96 additions & 95 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/indexed/thead/vlx.c
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65 changes: 33 additions & 32 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/indexed/thead/vsoxei16.c
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67 changes: 34 additions & 33 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/indexed/thead/vsoxei32.c
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57 changes: 29 additions & 28 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/indexed/thead/vsoxei64.c
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51 changes: 26 additions & 25 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/indexed/thead/vsoxei8.c
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191 changes: 96 additions & 95 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/indexed/thead/vsx.c
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191 changes: 96 additions & 95 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/indexed/wrappers/vlx.c
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191 changes: 96 additions & 95 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/indexed/wrappers/vsx.c
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1 change: 1 addition & 0 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-errors.c
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Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// RUN: %clang_cc1 %s -triple=riscv64 -target-feature +xtheadvector -fsyntax-only -verify

#include <riscv_vector.h>
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107 changes: 52 additions & 55 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-example-memcpy.c
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@@ -1,66 +1,63 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \
// RUN: -O0 -emit-llvm %s -o - | FileCheck %s

#include <riscv_vector.h>

typedef unsigned char uint8_t;

// CHECK-LABEL: define dso_local void @memcpy_v(ptr noundef %dst, ptr noundef %src, i32 noundef signext %n) #0 {
// CHECK-NEXT: entry:
// CHECK-NEXT: %dst.addr = alloca ptr, align 8
// CHECK-NEXT: %src.addr = alloca ptr, align 8
// CHECK-NEXT: %n.addr = alloca i32, align 4
// CHECK-NEXT: %vl = alloca i32, align 4
// CHECK-NEXT: %vec_src = alloca <vscale x 32 x i8>, align 1
// CHECK-NEXT: store ptr %dst, ptr %dst.addr, align 8
// CHECK-NEXT: store ptr %src, ptr %src.addr, align 8
// CHECK-NEXT: store i32 %n, ptr %n.addr, align 4
// CHECK-NEXT: br label %for.cond
// CHECK-LABEL: define dso_local void @memcpy_v
// CHECK-SAME: (ptr noundef [[DST:%.*]], ptr noundef [[SRC:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[DST_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[SRC_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[VL:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[VEC_SRC:%.*]] = alloca <vscale x 32 x i8>, align 1
// CHECK-NEXT: store ptr [[DST]], ptr [[DST_ADDR]], align 8
// CHECK-NEXT: store ptr [[SRC]], ptr [[SRC_ADDR]], align 8
// CHECK-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK-NEXT: br label [[FOR_COND:%.*]]
// CHECK: for.cond:
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 0
// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
// CHECK: for.body:
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64
// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.th.vsetvl.i64(i64 [[CONV]], i64 0, i64 2)
// CHECK-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK-NEXT: store i32 [[CONV1]], ptr [[VL]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SRC_ADDR]], align 8
// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[VL]], align 4
// CHECK-NEXT: [[CONV2:%.*]] = sext i32 [[TMP4]] to i64
// CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 32 x i8> @llvm.riscv.th.vle.nxv32i8.i64(<vscale x 32 x i8> poison, ptr [[TMP3]], i64 [[CONV2]])
// CHECK-NEXT: store <vscale x 32 x i8> [[TMP5]], ptr [[VEC_SRC]], align 1
// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP7:%.*]] = load <vscale x 32 x i8>, ptr [[VEC_SRC]], align 1
// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[VL]], align 4
// CHECK-NEXT: [[CONV3:%.*]] = sext i32 [[TMP8]] to i64
// CHECK-NEXT: call void @llvm.riscv.th.vse.nxv32i8.i64(<vscale x 32 x i8> [[TMP7]], ptr [[TMP6]], i64 [[CONV3]])
// CHECK-NEXT: br label [[FOR_INC:%.*]]
// CHECK: for.inc:
// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[VL]], align 4
// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], [[TMP9]]
// CHECK-NEXT: store i32 [[SUB]], ptr [[N_ADDR]], align 4
// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[VL]], align 4
// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[SRC_ADDR]], align 8
// CHECK-NEXT: [[IDX_EXT:%.*]] = sext i32 [[TMP11]] to i64
// CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, ptr [[TMP12]], i64 [[IDX_EXT]]
// CHECK-NEXT: store ptr [[ADD_PTR]], ptr [[SRC_ADDR]], align 8
// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[VL]], align 4
// CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DST_ADDR]], align 8
// CHECK-NEXT: [[IDX_EXT4:%.*]] = sext i32 [[TMP13]] to i64
// CHECK-NEXT: [[ADD_PTR5:%.*]] = getelementptr inbounds i8, ptr [[TMP14]], i64 [[IDX_EXT4]]
// CHECK-NEXT: store ptr [[ADD_PTR5]], ptr [[DST_ADDR]], align 8
// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
// CHECK: for.end:
// CHECK-NEXT: ret void
//
// CHECK-LABEL: for.cond: ; preds = %for.inc, %entry
// CHECK-NEXT: %0 = load i32, ptr %n.addr, align 4
// CHECK-NEXT: %cmp = icmp sgt i32 %0, 0
// CHECK-NEXT: br i1 %cmp, label %for.body, label %for.end
//
// CHECK-LABEL: for.body: ; preds = %for.cond
// CHECK-NEXT: %1 = load i32, ptr %n.addr, align 4
// CHECK-NEXT: %conv = sext i32 %1 to i64
// CHECK-NEXT: %2 = call i64 @llvm.riscv.th.vsetvl.i64(i64 %conv, i64 0, i64 2)
// CHECK-NEXT: %conv1 = trunc i64 %2 to i32
// CHECK-NEXT: store i32 %conv1, ptr %vl, align 4
// CHECK-NEXT: %3 = load ptr, ptr %src.addr, align 8
// CHECK-NEXT: %4 = load i32, ptr %vl, align 4
// CHECK-NEXT: %conv2 = sext i32 %4 to i64
// CHECK-NEXT: %5 = call <vscale x 32 x i8> @llvm.riscv.th.vle.nxv32i8.i64(<vscale x 32 x i8> poison, ptr %3, i64 %conv2)
// CHECK-NEXT: store <vscale x 32 x i8> %5, ptr %vec_src, align 1
// CHECK-NEXT: %6 = load ptr, ptr %dst.addr, align 8
// CHECK-NEXT: %7 = load <vscale x 32 x i8>, ptr %vec_src, align 1
// CHECK-NEXT: %8 = load i32, ptr %vl, align 4
// CHECK-NEXT: %conv3 = sext i32 %8 to i64
// CHECK-NEXT: call void @llvm.riscv.th.vse.nxv32i8.i64(<vscale x 32 x i8> %7, ptr %6, i64 %conv3)
// CHECK-NEXT: br label %for.inc
//
// CHECK-LABEL: for.inc: ; preds = %for.body
// CHECK-NEXT: %9 = load i32, ptr %vl, align 4
// CHECK-NEXT: %10 = load i32, ptr %n.addr, align 4
// CHECK-NEXT: %sub = sub nsw i32 %10, %9
// CHECK-NEXT: store i32 %sub, ptr %n.addr, align 4
// CHECK-NEXT: %11 = load i32, ptr %vl, align 4
// CHECK-NEXT: %12 = load ptr, ptr %src.addr, align 8
// CHECK-NEXT: %idx.ext = sext i32 %11 to i64
// CHECK-NEXT: %add.ptr = getelementptr inbounds i8, ptr %12, i64 %idx.ext
// CHECK-NEXT: store ptr %add.ptr, ptr %src.addr, align 8
// CHECK-NEXT: %13 = load i32, ptr %vl, align 4
// CHECK-NEXT: %14 = load ptr, ptr %dst.addr, align 8
// CHECK-NEXT: %idx.ext4 = sext i32 %13 to i64
// CHECK-NEXT: %add.ptr5 = getelementptr inbounds i8, ptr %14, i64 %idx.ext4
// CHECK-NEXT: store ptr %add.ptr5, ptr %dst.addr, align 8
// CHECK-NEXT: br label %for.cond, !llvm.loop !4
//
// CHECK-LABEL: for.end: ; preds = %for.cond
// CHECK-NEXT: ret void
// CHECK-NEXT: }

void memcpy_v(uint8_t *dst, const uint8_t *src, int n) {
for (int vl; n > 0; n -= vl, src += vl, dst += vl) {
vl = __riscv_vsetvl_e8m4(n);
Expand Down
31 changes: 16 additions & 15 deletions clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/strided/thead/vlsb.c
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Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | \
// RUN: opt -S -passes=mem2reg | \
Expand All @@ -16,7 +17,7 @@ vint8m1_t test_th_vlsb_v_i8m1(const int8_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_th_vlsb_v_i8m2
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.th.vlsb.nxv16i8.i64(<vscale x 16 x i8> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
Expand All @@ -26,7 +27,7 @@ vint8m2_t test_th_vlsb_v_i8m2(const int8_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_th_vlsb_v_i8m4
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.th.vlsb.nxv32i8.i64(<vscale x 32 x i8> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
Expand All @@ -36,7 +37,7 @@ vint8m4_t test_th_vlsb_v_i8m4(const int8_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_th_vlsb_v_i8m8
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.th.vlsb.nxv64i8.i64(<vscale x 64 x i8> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
Expand All @@ -46,7 +47,7 @@ vint8m8_t test_th_vlsb_v_i8m8(const int8_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_th_vlsb_v_i16m1
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.th.vlsb.nxv4i16.i64(<vscale x 4 x i16> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
Expand All @@ -56,7 +57,7 @@ vint16m1_t test_th_vlsb_v_i16m1(const int16_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_th_vlsb_v_i16m2
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.th.vlsb.nxv8i16.i64(<vscale x 8 x i16> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
Expand All @@ -66,7 +67,7 @@ vint16m2_t test_th_vlsb_v_i16m2(const int16_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_th_vlsb_v_i16m4
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.th.vlsb.nxv16i16.i64(<vscale x 16 x i16> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
Expand All @@ -76,7 +77,7 @@ vint16m4_t test_th_vlsb_v_i16m4(const int16_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_th_vlsb_v_i16m8
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.th.vlsb.nxv32i16.i64(<vscale x 32 x i16> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
Expand All @@ -86,7 +87,7 @@ vint16m8_t test_th_vlsb_v_i16m8(const int16_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_th_vlsb_v_i32m1
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vlsb.nxv2i32.i64(<vscale x 2 x i32> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
Expand All @@ -96,7 +97,7 @@ vint32m1_t test_th_vlsb_v_i32m1(const int32_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_th_vlsb_v_i32m2
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vlsb.nxv4i32.i64(<vscale x 4 x i32> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
Expand All @@ -106,7 +107,7 @@ vint32m2_t test_th_vlsb_v_i32m2(const int32_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_th_vlsb_v_i32m4
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vlsb.nxv8i32.i64(<vscale x 8 x i32> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
Expand All @@ -116,7 +117,7 @@ vint32m4_t test_th_vlsb_v_i32m4(const int32_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_th_vlsb_v_i32m8
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.th.vlsb.nxv16i32.i64(<vscale x 16 x i32> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
Expand All @@ -126,7 +127,7 @@ vint32m8_t test_th_vlsb_v_i32m8(const int32_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_th_vlsb_v_i64m1
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.th.vlsb.nxv1i64.i64(<vscale x 1 x i64> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
Expand All @@ -136,7 +137,7 @@ vint64m1_t test_th_vlsb_v_i64m1(const int64_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_th_vlsb_v_i64m2
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.th.vlsb.nxv2i64.i64(<vscale x 2 x i64> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
Expand All @@ -146,7 +147,7 @@ vint64m2_t test_th_vlsb_v_i64m2(const int64_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_th_vlsb_v_i64m4
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.th.vlsb.nxv4i64.i64(<vscale x 4 x i64> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
Expand All @@ -156,7 +157,7 @@ vint64m4_t test_th_vlsb_v_i64m4(const int64_t *base, size_t stride, size_t vl) {
}

// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_th_vlsb_v_i64m8
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[STRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.th.vlsb.nxv8i64.i64(<vscale x 8 x i64> poison, ptr [[BASE]], i64 [[STRIDE]], i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
Expand Down
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