Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[LLVM][XTHeadVector] support nvx1i1/nvx2i1/nvx4i1 operands for vector mask operations #120

Merged
merged 6 commits into from
Jun 24, 2024
Merged

[LLVM][XTHeadVector] support nvx1i1/nvx2i1/nvx4i1 operands for vector mask operations #120

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
6 commits
Select commit Hold shift + click to select a range
276a28f
[LLVM][XTHeadVector] support `vbool16/32/64` for vector mask operations
imkiva Jun 19, 2024
1a276de
[LLVM][XTHeadVector] correctly expand pseudos for `vmset/vmclr`
imkiva Jun 19, 2024
608e6d7
[LLVM][XTHeadVector] update corresponding tests
imkiva Jun 19, 2024
a49f805
[LLVM][XTHeadVector] update tests for `vmsof/vmsbf/vmsif`
imkiva Jun 21, 2024
c806b02
[LLVM][XTHeadVector] update tests for `vmfirst/vmpopc`
imkiva Jun 21, 2024
4a2deae
[LLVM][XTHeadVector] update tests for `vmfirst/vmpopc`
imkiva Jun 21, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
14 changes: 10 additions & 4 deletions llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -146,18 +146,24 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
case RISCV::PseudoVMSET_M_B64:
// vmset.m vd => vmxnor.mm vd, vd, vd
return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
case RISCV::PseudoTH_VMCLR_M_B1:
case RISCV::PseudoTH_VMCLR_M_B2:
case RISCV::PseudoTH_VMCLR_M_B4:
case RISCV::PseudoTH_VMCLR_M_B8:
case RISCV::PseudoTH_VMCLR_M_B16:
case RISCV::PseudoTH_VMCLR_M_B32:
case RISCV::PseudoTH_VMCLR_M_B64:
// th.vmclr.m vd => th.vmxor.mm vd, vd, vd
return expandVMSET_VMCLR(MBB, MBBI, RISCV::TH_VMXOR_MM);
// th.vmclr.m vd => th.vmxor.mm vd, vd, vd
return expandVMSET_VMCLR(MBB, MBBI, RISCV::TH_VMXOR_MM);
case RISCV::PseudoTH_VMSET_M_B1:
case RISCV::PseudoTH_VMSET_M_B2:
case RISCV::PseudoTH_VMSET_M_B4:
case RISCV::PseudoTH_VMSET_M_B8:
case RISCV::PseudoTH_VMSET_M_B16:
case RISCV::PseudoTH_VMSET_M_B32:
case RISCV::PseudoTH_VMSET_M_B64:
// th.vmset.m vd => th.vmxnor.mm vd, vd, vd
return expandVMSET_VMCLR(MBB, MBBI, RISCV::TH_VMXNOR_MM);
// th.vmset.m vd => th.vmxnor.mm vd, vd, vd
return expandVMSET_VMCLR(MBB, MBBI, RISCV::TH_VMXNOR_MM);
}

return false;
Expand Down
35 changes: 26 additions & 9 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -145,15 +145,32 @@ defset list<VTypeInfoToWide> AllWidenableIntToFloatXVectors = {
def : VTypeInfoToWide<VI32M4, VF64M8>;
}

class XMTypeInfo<ValueType Mas, int Sew, int Log2Sew, LMULInfo M, string Bx> {
ValueType Mask = Mas;
// {SEW, VLMul} values set a valid VType to deal with this mask type.
int SEW = Sew;
int Log2SEW = Log2Sew;
LMULInfo LMul = M;
string BX = Bx; // Appendix of mask operations.
// The pattern fragment which produces the AVL operand, representing the
// "natural" vector length for this mask type. For scalable masks this is
// VLMax.
OutPatFrag AVL = VLMax;
}

// Redefine `AllMasks` from RISCVInstrInfoVPseudos.td to remove fractionally-grouped register groups.
// TODO: riscv-v-intrinsics.pdf declares there are functions accepting vbool<16,32,64>_t, but they need
// to be connected to MF2, MF4, MF8, which are not supported by the 'V' extension 0.7.1.
defset list<MTypeInfo> AllXMasks = {
defset list<XMTypeInfo> AllXMasks = {
// vbool<n>_t, <n> = SEW/LMUL, we assume SEW=8 and corresponding LMUL.
def : MTypeInfo<vbool8_t, V_M1, "B8">;
def : MTypeInfo<vbool4_t, V_M2, "B16">;
def : MTypeInfo<vbool2_t, V_M4, "B32">;
def : MTypeInfo<vbool1_t, V_M8, "B64">;
def : XMTypeInfo<vbool8_t, 8, 3, V_M1, "B8">;
def : XMTypeInfo<vbool4_t, 8, 3, V_M2, "B16">;
def : XMTypeInfo<vbool2_t, 8, 3, V_M4, "B32">;
def : XMTypeInfo<vbool1_t, 8, 3, V_M8, "B64">;

// Cannot assume SEW=8, as <n> = SEW/LMUL, so LMUL = MF2/MF4/MF8, which is not supported.
// Instead, we assume LMUL=1, so SEW = <n> * LMUL.
def : XMTypeInfo<vbool64_t, 64, 6, V_M1, "B1">;
def : XMTypeInfo<vbool32_t, 32, 5, V_M1, "B2">;
def : XMTypeInfo<vbool16_t, 16, 4, V_M1, "B4">;
}

class GetXVTypePredicates<VTypeInfo vti> {
Expand Down Expand Up @@ -3981,7 +3998,7 @@ multiclass XVPatUnaryS_M<string intrinsic_name,

class XVPatMaskUnaryNoMask<string intrinsic_name,
string inst,
MTypeInfo mti> :
XMTypeInfo mti> :
Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name)
(mti.Mask VR:$rs2),
VLOpFrag)),
Expand All @@ -3992,7 +4009,7 @@ class XVPatMaskUnaryNoMask<string intrinsic_name,

class XVPatMaskUnaryMask<string intrinsic_name,
string inst,
MTypeInfo mti> :
XMTypeInfo mti> :
Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name#"_mask")
(mti.Mask VR:$merge),
(mti.Mask VR:$rs2),
Expand Down
60 changes: 60 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv0p71/vmand.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,66 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
; RUN: -verify-machineinstrs | FileCheck %s

declare <vscale x 1 x i1> @llvm.riscv.th.vmand.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
iXLen);

define <vscale x 1 x i1> @intrinsic_vmand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1
; CHECK-NEXT: th.vmand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.th.vmand.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
iXLen %2)

ret <vscale x 1 x i1> %a
}

declare <vscale x 2 x i1> @llvm.riscv.th.vmand.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
iXLen);

define <vscale x 2 x i1> @intrinsic_vmand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1
; CHECK-NEXT: th.vmand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.th.vmand.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
iXLen %2)

ret <vscale x 2 x i1> %a
}

declare <vscale x 4 x i1> @llvm.riscv.th.vmand.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
iXLen);

define <vscale x 4 x i1> @intrinsic_vmand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1
; CHECK-NEXT: th.vmand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.th.vmand.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
iXLen %2)

ret <vscale x 4 x i1> %a
}

declare <vscale x 8 x i1> @llvm.riscv.th.vmand.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
Expand Down
76 changes: 68 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv0p71/vmandn.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4,13 +4,73 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
; RUN: -verify-machineinstrs | FileCheck %s

declare <vscale x 1 x i1> @llvm.riscv.th.vmandnot.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
iXLen);

define <vscale x 1 x i1> @intrinsic_vmandnot_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.th.vmandnot.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
iXLen %2)

ret <vscale x 1 x i1> %a
}

declare <vscale x 2 x i1> @llvm.riscv.th.vmandnot.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
iXLen);

define <vscale x 2 x i1> @intrinsic_vmandnot_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.th.vmandnot.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
iXLen %2)

ret <vscale x 2 x i1> %a
}

declare <vscale x 4 x i1> @llvm.riscv.th.vmandnot.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
iXLen);

define <vscale x 4 x i1> @intrinsic_vmandnot_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.th.vmandnot.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
iXLen %2)

ret <vscale x 4 x i1> %a
}

declare <vscale x 8 x i1> @llvm.riscv.th.vmandnot.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
iXLen);

define <vscale x 8 x i1> @intrinsic_vmandn_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv8i1:
define <vscale x 8 x i1> @intrinsic_vmandnot_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m1, d1
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
Expand All @@ -29,8 +89,8 @@ declare <vscale x 16 x i1> @llvm.riscv.th.vmandnot.nxv16i1(
<vscale x 16 x i1>,
iXLen);

define <vscale x 16 x i1> @intrinsic_vmandn_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv16i1:
define <vscale x 16 x i1> @intrinsic_vmandnot_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m2, d1
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
Expand All @@ -49,8 +109,8 @@ declare <vscale x 32 x i1> @llvm.riscv.th.vmandnot.nxv32i1(
<vscale x 32 x i1>,
iXLen);

define <vscale x 32 x i1> @intrinsic_vmandn_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv32i1:
define <vscale x 32 x i1> @intrinsic_vmandnot_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m4, d1
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
Expand All @@ -69,8 +129,8 @@ declare <vscale x 64 x i1> @llvm.riscv.th.vmandnot.nxv64i1(
<vscale x 64 x i1>,
iXLen);

define <vscale x 64 x i1> @intrinsic_vmandn_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv64i1:
define <vscale x 64 x i1> @intrinsic_vmandnot_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandnot_mm_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e8, m8, d1
; CHECK-NEXT: th.vmandnot.mm v0, v0, v8
Expand Down
48 changes: 48 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv0p71/vmclr.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,54 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
; RUN: -verify-machineinstrs | FileCheck %s

declare <vscale x 1 x i1> @llvm.riscv.th.vmclr.nxv1i1(
iXLen);

define <vscale x 1 x i1> @intrinsic_vmclr_m_pseudo_nxv1i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e64, m1, d1
; CHECK-NEXT: th.vmclr.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.th.vmclr.nxv1i1(
iXLen %0)

ret <vscale x 1 x i1> %a
}

declare <vscale x 2 x i1> @llvm.riscv.th.vmclr.nxv2i1(
iXLen);

define <vscale x 2 x i1> @intrinsic_vmclr_m_pseudo_nxv2i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e32, m1, d1
; CHECK-NEXT: th.vmclr.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.th.vmclr.nxv2i1(
iXLen %0)

ret <vscale x 2 x i1> %a
}

declare <vscale x 4 x i1> @llvm.riscv.th.vmclr.nxv4i1(
iXLen);

define <vscale x 4 x i1> @intrinsic_vmclr_m_pseudo_nxv4i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: th.vsetvli zero, a0, e16, m1, d1
; CHECK-NEXT: th.vmclr.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.th.vmclr.nxv4i1(
iXLen %0)

ret <vscale x 4 x i1> %a
}

declare <vscale x 8 x i1> @llvm.riscv.th.vmclr.nxv8i1(
iXLen);

Expand Down
Loading
Loading