[LLVM][XTHeadVector] Implement intrinsics for vsadd{u}/vssub{u}.

README.md

@@ -53,6 +53,7 @@ Any feature not listed below but present in the specification should be consider
     - (Done) `12.13. Vector Widening Integer Multiply-Add Instructions`
     - (Done) `12.14. Vector Integer Merge and Move Instructions`
   - (WIP) `13. Vector Fixed-Point Arithmetic Instructions`
+    - (Done) `13.1. Vector Single-Width Saturating Add and Subtract`
     - (Done) `13.2. Vector Single-Width Averaging Add and Subtract`
     - (Done) `13.3. Vector Single-Width Fractional Multiply with Rounding and Saturation`
 - (WIP) Clang intrinsics related to the `XTHeadVector` extension:

llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td

@@ -668,6 +668,18 @@ let TargetPrefix = "riscv" in {
     let VLOperand = 4;
   }
 
+  // For Saturating binary operations with mask but no policy.
+  // The destination vector type is the same as first source vector.
+  // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl)
+  class XVSaturatingBinaryAAXMasked
+        : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+                    [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
+    let ScalarOperand = 2;
+    let VLOperand = 4;
+  }
+
   multiclass XVBinaryAAX {
     def "int_riscv_" # NAME : RISCVBinaryAAXUnMasked;
     def "int_riscv_" # NAME # "_mask" : XVBinaryAAXMasked;
@@ -702,6 +714,11 @@ let TargetPrefix = "riscv" in {
     def "int_riscv_" # NAME : XVTernaryWideUnMasked;
     def "int_riscv_" # NAME # "_mask" : XVTernaryWideMasked;
   }
+
+  multiclass XVSaturatingBinaryAAX {
+    def "int_riscv_" # NAME : RISCVSaturatingBinaryAAXUnMasked;
+    def "int_riscv_" # NAME # "_mask" : XVSaturatingBinaryAAXMasked;
+  }
 }
 
 let TargetPrefix = "riscv" in {
@@ -791,6 +808,12 @@ let TargetPrefix = "riscv" in {
   // 12.14. Vector Integer Merge and Move Instructions
   defm th_vmerge : RISCVBinaryWithV0;
 
+  // 13.1. Vector Single-Width Saturating Add and Subtract
+  defm th_vsaddu : XVSaturatingBinaryAAX;
+  defm th_vsadd : XVSaturatingBinaryAAX;
+  defm th_vssubu : XVSaturatingBinaryAAX;
+  defm th_vssub : XVSaturatingBinaryAAX;
+
   // 13.2. Vector Single-Width Averaging Add and Subtract
   defm th_vaadd : XVBinaryAAXRoundingMode;
   defm th_vasub : XVBinaryAAXRoundingMode;

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td

@@ -2694,6 +2694,39 @@ multiclass XVPatTernaryW_VX<string intrinsic, string instruction,
   }
 }
 
+multiclass XVPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
+  foreach m = MxListXTHeadV in {
+    defvar mx = m.MX;
+    defvar WriteVSALUV_MX = !cast<SchedWrite>("WriteVSALUV_" # mx);
+    defvar WriteVSALUX_MX = !cast<SchedWrite>("WriteVSALUX_" # mx);
+    defvar WriteVSALUI_MX = !cast<SchedWrite>("WriteVSALUI_" # mx);
+    defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
+    defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
+
+    defm "" : XVPseudoBinaryV_VV<m, Constraint>,
+              Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
+    defm "" : XVPseudoBinaryV_VX<m, Constraint>,
+              Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
+    defm "" : XVPseudoBinaryV_VI<ImmType, m, Constraint>,
+              Sched<[WriteVSALUI_MX, ReadVSALUV_MX, ReadVMask]>;
+  }
+}
+
+multiclass XVPseudoVSALU_VV_VX {
+  foreach m = MxListXTHeadV in {
+    defvar mx = m.MX;
+    defvar WriteVSALUV_MX = !cast<SchedWrite>("WriteVSALUV_" # mx);
+    defvar WriteVSALUX_MX = !cast<SchedWrite>("WriteVSALUX_" # mx);
+    defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
+    defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
+
+    defm "" : XVPseudoBinaryV_VV<m>,
+              Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
+    defm "" : XVPseudoBinaryV_VX<m>,
+              Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
+  }
+}
+
 multiclass XVPatBinaryV_VV_VX_VI<string intrinsic, string instruction,
                                  list<VTypeInfo> vtilist, Operand ImmType = simm5>
     : XVPatBinaryV_VV<intrinsic, instruction, vtilist>,
@@ -3210,6 +3243,23 @@ let Predicates = [HasVendorXTHeadV] in {
   }
 } // Predicates = [HasVendorXTHeadV]
 
+//===----------------------------------------------------------------------===//
+// 13.1. Vector Single-Width Averaging Add and Subtract
+//===----------------------------------------------------------------------===//
+let Defs = [VXSAT], hasSideEffects = 1, Predicates = [HasVendorXTHeadV] in {
+  defm PseudoTH_VSADDU : XVPseudoVSALU_VV_VX_VI;
+  defm PseudoTH_VSADD  : XVPseudoVSALU_VV_VX_VI;
+  defm PseudoTH_VSSUBU : XVPseudoVSALU_VV_VX;
+  defm PseudoTH_VSSUB  : XVPseudoVSALU_VV_VX;
+} // Predicates = [HasVendorXTHeadV]
+
+let Predicates = [HasVendorXTHeadV] in {
+  defm : XVPatBinaryV_VV_VX_VI<"int_riscv_th_vsaddu", "PseudoTH_VSADDU", AllIntegerXVectors>;
+  defm : XVPatBinaryV_VV_VX_VI<"int_riscv_th_vsadd", "PseudoTH_VSADD", AllIntegerXVectors>;
+  defm : XVPatBinaryV_VV_VX<"int_riscv_th_vssubu", "PseudoTH_VSSUBU", AllIntegerXVectors>;
+  defm : XVPatBinaryV_VV_VX<"int_riscv_th_vssub", "PseudoTH_VSSUB", AllIntegerXVectors>;
+}
+
 //===----------------------------------------------------------------------===//
 // 13.2. Vector Single-Width Averaging Add and Subtract
 //===----------------------------------------------------------------------===//