Merge pull request #2 from inspireMeNow/test

riscv: Add support for riscv64ilp32 (X32 ABI)
ruyisdk · Apr 29, 2024 · f946be9 · f946be9
2 parents 20a1b34 + 463fa7c
commit f946be9
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Showing 21 changed files with 76 additions and 18 deletions.
diff --git a/configs/devices/riscv64ilp32-softmmu/default.mak b/configs/devices/riscv64ilp32-softmmu/default.mak
@@ -0,0 +1,16 @@
+# Default configuration for riscv64-softmmu
+
+# Uncomment the following lines to disable these optional devices:
+#
+#CONFIG_PCI_DEVICES=n
+CONFIG_SEMIHOSTING=y
+CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
+
+# Boards:
+#
+CONFIG_SPIKE=y
+CONFIG_SIFIVE_E=y
+CONFIG_SIFIVE_U=y
+CONFIG_RISCV_VIRT=y
+CONFIG_MICROCHIP_PFSOC=y
+CONFIG_SHAKTI_C=y
diff --git a/configs/targets/riscv64ilp32-linux-user.mak b/configs/targets/riscv64ilp32-linux-user.mak
@@ -0,0 +1,6 @@
+TARGET_ARCH=riscv64ilp32
+TARGET_BASE_ARCH=riscv
+TARGET_ABI_DIR=riscv
+TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
+CONFIG_SEMIHOSTING=y
+CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/configs/targets/riscv64ilp32-softmmu.mak b/configs/targets/riscv64ilp32-softmmu.mak
@@ -0,0 +1,5 @@
+TARGET_ARCH=riscv64ilp32
+TARGET_BASE_ARCH=riscv
+TARGET_SUPPORTS_MTTCG=y
+TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
+TARGET_NEED_FDT=y
diff --git a/configure b/configure
@@ -530,7 +530,7 @@ case "$cpu" in
     CPU_CFLAGS="-m64 -mlittle-endian"
     ;;
 
-  riscv32 | riscv64)
+  riscv32 | riscv64 | riscv64ilp32)
     host_arch=riscv
     linux_arch=riscv
     ;;

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
@@ -68,11 +68,15 @@ char *riscv_plic_hart_config_string(int hart_count)
 
 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
                                           target_ulong firmware_end_addr) {
+    #ifdef TARGET_RISCV64ILP32
+    return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
+    #else
     if (riscv_is_32bit(harts)) {
         return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
     } else {
         return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
     }
+    #endif
 }
 
 const char *riscv_default_firmware_name(RISCVHartArrayState *harts)

diff --git a/include/elf.h b/include/elf.h
@@ -1447,6 +1447,7 @@ typedef struct {
 #define EF_RISCV_FLOAT_ABI_QUAD   0x0006
 #define EF_RISCV_RVE              0x0008
 #define EF_RISCV_TSO              0x0010
+#define EF_RISCV_X32              0x0020
 
 typedef struct elf32_rel {
   Elf32_Addr r_offset;

diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h
@@ -23,7 +23,7 @@
 #if defined(TARGET_RISCV32)
 #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
 #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
-#elif defined(TARGET_RISCV64)
+#elif defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
 #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
 #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
 #endif

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
@@ -1697,7 +1697,11 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
 #define ELF_START_MMAP 0x80000000
 #define ELF_ARCH  EM_RISCV
 
-#ifdef TARGET_RISCV32
+#ifndef ABI_X32_P
+#define ABI_X32_P(e_flags) ((e_flags & EF_RISCV_X32) != 0)
+#endif
+
+#if defined(TARGET_RISCV32) || defined(TARGET_RISCV64ILP32)
 #define ELF_CLASS ELFCLASS32
 #else
 #define ELF_CLASS ELFCLASS64
@@ -2058,6 +2062,9 @@ static bool elf_check_ident(struct elfhdr *ehdr)
             && ehdr->e_ident[EI_MAG1] == ELFMAG1
             && ehdr->e_ident[EI_MAG2] == ELFMAG2
             && ehdr->e_ident[EI_MAG3] == ELFMAG3
+            #ifdef TARGET_RISCV64ILP32
+            && ABI_X32_P(ehdr->e_flags)
+            #endif
             && ehdr->e_ident[EI_CLASS] == ELF_CLASS
             && ehdr->e_ident[EI_DATA] == ELF_DATA
             && ehdr->e_ident[EI_VERSION] == EV_CURRENT);

diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig
@@ -3,3 +3,6 @@ config RISCV32
 
 config RISCV64
     bool
+
+config RISCV64ILP32
+    bool
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
@@ -12,6 +12,10 @@
 # define TARGET_LONG_BITS 64
 # define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
 # define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
+#elif defined(TARGET_RISCV64ILP32)
+# define TARGET_LONG_BITS 64
+# define TARGET_PHYS_ADDR_SPACE_BITS 31
+# define TARGET_VIRT_ADDR_SPACE_BITS 31
 #elif defined(TARGET_RISCV32)
 # define TARGET_LONG_BITS 32
 # define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
@@ -46,7 +46,7 @@
 
 #if defined(TARGET_RISCV32)
 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
-#elif defined(TARGET_RISCV64)
+#elif defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
 #endif
 

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
@@ -367,7 +367,7 @@ static void riscv_any_cpu_init(Object *obj)
     CPURISCVState *env = &cpu->env;
 #if defined(TARGET_RISCV32)
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
-#elif defined(TARGET_RISCV64)
+#elif defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 #endif
 
@@ -386,7 +386,7 @@ static void riscv_any_cpu_init(Object *obj)
     cpu->cfg.pmp = true;
 }
 
-#if defined(TARGET_RISCV64)
+#if defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
 static void rv64_base_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -613,7 +613,7 @@ static void riscv_host_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
 #if defined(TARGET_RISCV32)
     set_misa(env, MXL_RV32, 0);
-#elif defined(TARGET_RISCV64)
+#elif defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
     set_misa(env, MXL_RV64, 0);
 #endif
     riscv_cpu_add_user_properties(obj);
@@ -1040,7 +1040,7 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
 
     /* Validate that MISA_MXL is set properly. */
     switch (env->misa_mxl_max) {
-#ifdef TARGET_RISCV64
+#if defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
     case MXL_RV64:
     case MXL_RV128:
         cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
@@ -2290,7 +2290,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32_sifive_e_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32_sifive_u_cpu_init),
-#elif defined(TARGET_RISCV64)
+#elif defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64,   rv64_base_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
@@ -70,7 +70,11 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     RISCVExtStatus fs, vs;
     uint32_t flags = 0;
 
+    #ifdef TARGET_RISCV64ILP32
+    *pc = env->pc & UINT32_MAX;
+    #else
     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
+    #endif
     *cs_base = 0;
 
     if (cpu->cfg.ext_zve32f) {
@@ -189,6 +193,10 @@ void riscv_cpu_update_mask(CPURISCVState *env)
         env->cur_pmmask = mask;
         env->cur_pmbase = base;
     }
+
+#ifdef TARGET_RISCV64ILP32
+    env->cur_pmmask = 0xffffffff00000000ULL;
+#endif
 }
 
 #ifndef CONFIG_USER_ONLY

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
@@ -1377,7 +1377,7 @@ static RISCVException read_misa(CPURISCVState *env, int csrno,
     case MXL_RV32:
         misa = (target_ulong)MXL_RV32 << 30;
         break;
-#ifdef TARGET_RISCV64
+#if defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
     case MXL_RV64:
         misa = (target_ulong)MXL_RV64 << 62;
         break;

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
@@ -56,7 +56,11 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
     if (n < 32) {
         tmp = env->gpr[n];
     } else if (n == 32) {
+        #ifdef TARGET_RISCV64ILP32
+        tmp = env->pc & UINT32_MAX;
+        #else
         tmp = env->pc;
+        #endif
     } else {
         return 0;
     }

diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -523,7 +523,7 @@ static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-#ifdef TARGET_RISCV64
+#if defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
     gen_set_gpr(ctx, a->rd, cpu_fpr[a->rs1]);
     return true;
 #else
@@ -573,7 +573,7 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-#ifdef TARGET_RISCV64
+#if defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
     tcg_gen_mov_tl(cpu_fpr[a->rd], get_gpr(ctx, a->rs1, EXT_NONE));
     mark_fs_dirty(ctx);
     return true;

diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -420,7 +420,7 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
 
     TCGv dest = dest_gpr(ctx, a->rd);
     TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
-#if defined(TARGET_RISCV64)
+#if defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
     tcg_gen_ext32s_tl(dest, src1);
 #else
     tcg_gen_extrl_i64_i32(dest, src1);

diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -578,7 +578,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
 
     TCGv dest = dest_gpr(ctx, a->rd);
 
-#if defined(TARGET_RISCV64)
+#if defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
     /* 16 bits -> 64 bits */
     tcg_gen_ext16s_tl(dest, cpu_fpr[a->rs1]);
 #else

diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
@@ -37,7 +37,7 @@
 /* Perform linear address sign extension */
 static target_ulong addr_canonical(int va_bits, target_ulong addr)
 {
-#ifdef TARGET_RISCV64
+#if defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
     if (addr & (1UL << (va_bits - 1))) {
         addr |= (hwaddr)-(1L << va_bits);
     }

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
@@ -471,7 +471,7 @@ static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num)
         tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]);
         return t;
     }
-#ifdef TARGET_RISCV64
+#if defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
     case MXL_RV64:
         return cpu_gpr[reg_num];
 #endif
@@ -493,7 +493,7 @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num)
     switch (get_xl(ctx)) {
     case MXL_RV32:
         return tcg_temp_new_i64();
-#ifdef TARGET_RISCV64
+#if defined(TARGET_RISCV64) || defined(TARGET_RISCV64ILP32)
     case MXL_RV64:
         return cpu_gpr[reg_num];
 #endif

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
@@ -235,7 +235,7 @@ static inline int vext_elem_mask(void *v0, int index)
 }
 
 /* elements operations for load and store */
-typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr,
+typedef void vext_ldst_elem_fn(CPURISCVState *env, abi_ptr addr,
                                uint32_t idx, void *vd, uintptr_t retaddr);
 
 #define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF)            \
-Original file line number
+Diff line change
@@ Expand Up / @@ -3,3 +3,6 @@ config RISCV32 @@
     config RISCV64
         bool
+    config RISCV64ILP32
+        bool