PFM/D/kv260: update to 23.2

Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md

@@ -8,13 +8,13 @@
 
 # Vitis Custom Embedded Platform Creation Example on KV260
 
-***Version: Vitis 2023.1***
+***Version: Vitis 2023.2***
 
 The [AMD Kria™ KV260 Vision AI Starter Kit](https://www.xilinx.com/products/som/kria/kv260-vision-starter-kit.html) is the development platform for Kria K26 SOM. The KV260 is built for advanced vision application development without requiring complex hardware design knowledge. It is based on the AMD UltraScale+™ MPSoC technology similar to ZCU104 evaluation board. In this example, you will extend the [ZCU104 custom embedded platform creation example](../02-Edge-AI-ZCU104/) to KV260 Vision AI Starter Kit.
 
 To highlight the differences between KV260 and ZCU104, this example will simplify the descriptions of general steps that are shared between all MPSoC platforms, but add more KV260 specific contents. If you have question in some steps, cross reference [ZCU104 custom embedded platform creation example](../02-Edge-AI-ZCU104/), or ask questions in Github Issues page.
 
-For your reference, this example total system structure is similar to the following figure.
+For your reference, The structure of this example system is shown in the following figure..
 
 ![missing image](./images/structure.svg)
 
@@ -77,7 +77,7 @@ The platform creation steps are introduced in the following pages. Each page des
   - [Setting up the Vitis environment](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/settingupvitisenvironment.html)
   - [Installing Xilinx Runtime](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/pjr1542153622642.html)
 - Platform Examples
-  - [zcu102](https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2023.1/Xilinx_Official_Platforms/xilinx_zcu102_base) and [zcu104](https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2023.1/Xilinx_Official_Platforms/xilinx_zcu104_base) base platform source code in [Vitis Embedded Platform Source Github Repository](https://github.com/Xilinx/Vitis_Embedded_Platform_Source)
+  - [zcu102](https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2023.2/Xilinx_Official_Platforms/xilinx_zcu102_base) and [zcu104](https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2023.2/Xilinx_Official_Platforms/xilinx_zcu104_base) base platform source code in [Vitis Embedded Platform Source Github Repository](https://github.com/Xilinx/Vitis_Embedded_Platform_Source)
 - [Xilinx Run Time (XRT)](https://xilinx.github.io/XRT/master/html/index.html)
 - [Vitis-AI GitHub Repository](https://github.com/Xilinx/Vitis-AI)
 

Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/description.json

@@ -26,7 +26,7 @@
             }
         ],
         "targets": [
-
+            "vitis_hw_build"  
         ],
         "custom_build_target":
         {

Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/Makefile

@@ -11,10 +11,10 @@ VERSION=2023.2
 COMMON_IMAGE_ZYNQMP ?=${PLATFORM_REPO_PATHS}/sw/zynqmp/xilinx-zynqmp-common-v$(VERSION)/
 DT_PLAT_NAME=mydeivice
 DT_PATH=$(ROOT_DIR)/$(DT_PLAT_NAME)/psu_cortexa53_0/device_tree_domain/bsp
-BOOT=boot
-SD_DIR=sd_dir
+DTB =$(ROOT_DIR)/$(DT_PLAT_NAME)/psu_cortexa53_0/device_tree_domain/bsp/system.dtb
+
 SYSROOT=sysroot
-SW_COMP=sw_comp
+
 
 .PHONY: help 
 
@@ -23,7 +23,7 @@ help:
 	@echo "make all COMMON_IMAGE_ZYNQMP=<path/to/common_image/>  	## Generate platform with pre-built software components"
 
 
-all: check-common-image sw_comps dtb dtbo pfm_fsbl pfm sysroot
+all: check-common-image dtb dtbo pfm sysroot
 
 #target : check  whether the common image is ready 
 check-common-image:
@@ -33,41 +33,31 @@ ifeq ($(wildcard $(COMMON_IMAGE_ZYNQMP)/Image),)
 	@echo "exit ....." && exit 1
 endif
 
-#target :software components
-#copy software components to local directory
-sw_comps:$(COMMON_IMAGE_ZYNQMP)/Image
-	@echo "create folder to store sw components and copy software components to local directory ./boot and ./sd_dir"
-	mkdir -p $(SW_COMP) && mkdir  -p $(BOOT) && mkdir  -p $(SD_DIR)
-	cp $(COMMON_IMAGE_ZYNQMP)/u-boot.elf  $(BOOT)/
-	cp $(COMMON_IMAGE_ZYNQMP)/bl31.elf  $(BOOT)/
-	cp $(COMMON_IMAGE_ZYNQMP)/boot.scr $(SD_DIR)/
-	cp $(COMMON_IMAGE_ZYNQMP)/Image  $(SW_COMP)/
-	cp $(COMMON_IMAGE_ZYNQMP)/rootfs.ext4  $(SW_COMP)/
 
 
 dtb:
 	@echo "execute createdts to generate dtb file"
 	xsct -eval " createdts -hw ../step1_vivado/build/vivado/$(XSA_NAME).xsa -zocl  -platform-name $(DT_PLAT_NAME) -out .  -git-branch xlnx_rel_v2023.1  -overlay -compile"
-	cp $(DT_PATH)/system.dtb $(BOOT)/
-	cp $(DT_PATH)/system.dtb $(SD_DIR)/
 
 dtbo:$(DT_PATH)/pl.dtsi
 	dtc -@ -O dtb -o $(DT_PATH)/pl.dtbo $(DT_PATH)/pl.dtsi
 	mkdir -p dtbo_output && cp $(DT_PATH)/pl.dtbo dtbo_output/
 
-pfm_fsbl:
-	@echo "INFO: Creating simple Platform $(PLATFORM_NAME_FSBL) to get FSBL and PMU"
-#FSBL option is to convince XSCT to create a simple platform to get FSBL and PMU.
-	xsct xsct_create_pfm.tcl  $(PLATFORM_NAME_FSBL)  $(XSA_NAME)  ../step1_vivado/build/vivado fsbl
-	@echo "INFO: Checking created platforms:" && find . -name "*.xpfm"
 
 #create platfrom 
 pfm:
-	cp $(PLATFORM_NAME_FSBL)/zynqmp_fsbl/fsbl_a53.elf $(BOOT)/fsbl.elf
-	cp $(PLATFORM_NAME_FSBL)/zynqmp_pmufw/pmufw.elf $(BOOT)/
-	@echo "INFO: Creating Final Platform $(PLATFORM_NAME)"
-	xsct xsct_create_pfm.tcl $(PLATFORM_NAME) $(XSA_NAME) ../step1_vivado/build/vivado
+
+	@echo "INFO: Creating  Platform $(PLATFORM_NAME)"
+	mkdir tmp -p  && set %XILINX_VITIS_DATA_DIR%="tmp/"
+	vitis -s platform_creation.py --platform_name $(PLATFORM_NAME) --xsa_path ../step1_vivado/build/vivado/$(XSA_NAME).xsa --boot $(COMMON_IMAGE_ZYNQMP) --dtb $(DTB)
 	@echo "INFO: Checking created platforms:" && find . -name "*.xpfm"
+#install SDK tool
+sysroot: $(SYSROOT)
+
+$(SYSROOT): $(COMMON_IMAGE_ZYNQMP)/sdk.sh
+	mkdir -p $(SYSROOT) && sh $(COMMON_IMAGE_ZYNQMP)/sdk.sh -d  $(SYSROOT)/ -y
+
+
 
 #install SDK tool
 sysroot: $(SYSROOT)
@@ -76,7 +66,7 @@ $(SYSROOT): $(COMMON_IMAGE_ZYNQMP)/sdk.sh
 	mkdir -p $(SYSROOT) && sh $(COMMON_IMAGE_ZYNQMP)/sdk.sh -d  $(SYSROOT)/ -y
 
 clean:
-	$(RM) -r IDE.log $(PLATFORM_NAME) $(PLATFORM_NAME_FSBL) device-tree-xlnx  mydevice dt_output dtg boot sd_dir dtbo_output
+	$(RM) -r IDE.log $(PLATFORM_NAME) $(PLATFORM_NAME_FSBL) device-tree-xlnx  mydevice dt_output dtg dtbo_output
 
 ultraclean: clean
-	$(RM) -r sw_comp  sysroot
+	$(RM) -r   sysroot

Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/platform_creation.py

@@ -0,0 +1,33 @@
+#/*
+#Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
+#SPDX-License-Identifier: X11
+#*/
+
+# 2023-04-02T21:02:13.258137
+import vitis
+import argparse
+import os
+
+print("Platform generation")
+parser = argparse.ArgumentParser()
+parser.add_argument("--platform_name", type=str, dest="platform_name")
+parser.add_argument("--xsa_path", type=str, dest="xsa_path")
+parser.add_argument("--boot", type=str, dest="boot")
+parser.add_argument("--dtb", type=str, dest="dtb")
+args = parser.parse_args()
+platform_name=args.platform_name
+xsa_path=args.xsa_path
+dtb=args.dtb
+boot=args.boot
+print('args',args)
+client = vitis.create_client()
+client.set_workspace(path=os.getcwd())
+platform = client.create_platform_component(name = platform_name, hw =xsa_path, os = "linux",cpu = "psu_cortexa53" )
+platform = client.get_platform_component(name=platform_name)
+domain = platform.get_domain(name="linux_psu_cortexa53")
+status = domain.update_name(new_name="xrt")
+status = domain.generate_bif() 
+status = domain.add_boot_dir(path=boot)
+status = domain.set_dtb(path=dtb)
+
+status = platform.build()

Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step3_validate/Makefile

@@ -8,7 +8,8 @@ PLATFORM_NAME=kv260_custom
 PLATFORM= $(ROOT_DIR)/../step2_pfm/$(PLATFORM_NAME)/export/$(PLATFORM_NAME)/$(PLATFORM_NAME).xpfm
 SW_COMP = $(ROOT_DIR)/../step2_pfm/sw_comp/
 SYSROOTDIR=$(ROOT_DIR)/../step2_pfm/sysroot/
-
+VERSION=2023.2
+COMMON_IMAGE_ZYNQMP ?=${PLATFORM_REPO_PATHS}/sw/zynqmp/xilinx-zynqmp-common-v$(VERSION)/
 PL_EXAMPLE_PATH = Vitis_Accel_Examples/cpp_kernels/simple_vadd/
 
 .PHONY: help  
@@ -29,11 +30,11 @@ Vitis_Accel_Examples:
 
 # Quick command for generating vadd hw xclbin
 vadd_hw: Vitis_Accel_Examples
-	$(MAKE) -C $(PL_EXAMPLE_PATH) all TARGET=hw PLATFORM=$(PLATFORM) HOST_ARCH=aarch64 DEV_ARCH=zynquplus EDGE_COMMON_SW=$(SW_COMP) SYSROOT=$(SYSROOTDIR)/sysroots/cortexa72-cortexa53-xilinx-linux
+	$(MAKE) -C $(PL_EXAMPLE_PATH) all TARGET=hw PLATFORM=$(PLATFORM) HOST_ARCH=aarch64 DEV_ARCH=zynquplus EDGE_COMMON_SW=$(COMMON_IMAGE_ZYNQMP) SYSROOT=$(SYSROOTDIR)/sysroots/cortexa72-cortexa53-xilinx-linux
 # vadd_hw generates the files for running on hardware. User needs to pick the files required by KV260, rename thr file and transfer them to the board
 # Do not use the generated sd_card.img
 $(PL_EXAMPLE_PATH)/simple_vadd:   Vitis_Accel_Examples $(PLATFORM)  
-	$(MAKE) -C $(PL_EXAMPLE_PATH) all TARGET=hw PLATFORM=$(PLATFORM) DEV_ARCH=zynquplus HOST_ARCH=aarch64 EDGE_COMMON_SW=$(SW_COMP) SYSROOT=$(SYSROOTDIR)/sysroots/cortexa72-cortexa53-xilinx-linux
+	$(MAKE) -C $(PL_EXAMPLE_PATH) all TARGET=hw PLATFORM=$(PLATFORM) DEV_ARCH=zynquplus HOST_ARCH=aarch64 EDGE_COMMON_SW=$(COMMON_IMAGE_ZYNQMP) SYSROOT=$(SYSROOTDIR)/sysroots/cortexa72-cortexa53-xilinx-linux
 
 
 $(PL_EXAMPLE_PATH)/shell.json:

Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step1.md

@@ -1,6 +1,6 @@
 <table class="sphinxhide" width="100%">
  <tr width="100%">
-    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>2023.1 Vitis™ Platform Creation Tutorials</h1>
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>2023.2 Vitis™ Platform Creation Tutorials</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
     </td>
  </tr>