Skip to content

Commit

Permalink
TDL: Edits and rebranding
Browse files Browse the repository at this point in the history
  • Loading branch information
ryanvergel authored and GitHub Enterprise committed Dec 3, 2023
1 parent efabd14 commit 99ee264
Show file tree
Hide file tree
Showing 58 changed files with 839 additions and 1,005 deletions.
14 changes: 7 additions & 7 deletions AI_Engine_Development/AIE-ML/AIE-ML.rst
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
#######################################
AI Engine Development
#######################################
##############################################################################
AI Engine for Machine Learning Development
##############################################################################


.. sidebar:: More Information
Expand All @@ -16,7 +16,7 @@ The tutorials under the AI Engine for Machine Learning (AIE-ML) Development help

.. important::

Before beginning a tutorial, ensure you have installed the Vitis 2023.2 software. The Vitis release includes all the embedded base platforms, including the VEK280 ES1 base platform that is used in these tutorials. In addition, ensure you have downloaded the Common Images for Embedded Vitis Platforms from `Downloads <https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html>`_ .
Before beginning a tutorial, ensure you have installed the Vitis 2023.2 software. The Vitis release includes all the embedded base platforms, including the VEK280 ES1 base platform that is used in these tutorials. In addition, ensure you have downloaded the Common Images for Embedded Vitis Platforms from `Downloads <https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html>`_.

The `common image` package contains a prebuilt Linux kernel and root file system that can be used with the AMD Versal™ board for embedded design development using the Vitis software platform.

Expand All @@ -29,7 +29,7 @@ Before starting a tutorial, run the following steps:



.. note::
.. note::

These tutorials target VEK280 ES1 board or build custom board using ES devices, which are subject to a special license, please obtain a license for using Beta Devices in AMD tools, and make sure it's enabled by executing `enable_beta_device` (or add it to the tools initial ``.tcl`` files).

Expand All @@ -47,7 +47,7 @@ These tutorials target the **VEK280 ES1** board. The table below lists the tutor
:caption: Feature Tutorials
:hidden:

Feature Tutorials <./docs/Feature_Tutorials/Feature_Tutorials>
Feature Tutorials <./Feature_Tutorials/Feature_Tutorials>

.. csv-table:: Feature Tutorials
:header: "Tutorial","Platform","OS","IDE Flow","Libraries Used","HLS Kernel","x86 simulator","aie simulator","SW Emu","HW Emu","HW","Event Trace in HW","Profile in HW"
Expand All @@ -72,7 +72,7 @@ These tutorials target the **VEK280 ES1** board. The table below lists the tutor
:caption: Design Tutorials
:hidden:

Design Tutorials <./docs/Design_Tutorials/Design_Tutorials>
Design Tutorials <./Design_Tutorials/Design_Tutorials>



Expand Down
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
<!-- <table class="sphinxhide" width="100%"> -->
<table class="sphinxhide" width="100%">
<tr width="100%">
<td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>AI Engine Development</h1>
<td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>AIE-ML Development</h1>
<a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
<a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis™ AI Development Environment on xilinx.com</a>
<a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis™ AI Development Environment on xilinx.com</br></a>
</td>
</tr>
</table>
Expand Down
Original file line number Diff line number Diff line change
@@ -1,18 +1,18 @@
<!-- <table class="sphinxhide" width="100%"> -->
<table class="sphinxhide" width="100%">
<tr width="100%">
<td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>AI Engine Development</h1>
<td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>AIE-ML Development</h1>
<a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
<a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis™ AI Development Environment on xilinx.com</a>
<a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis™ AI Development Environment on xilinx.com</br></a>
</td>
</tr>
</table>

# Compute Optimization

## _AI Engine-ML_ matrix multiplication Instruction Set
## AI Engine-ML matrix multiplication Instruction Set


The _AI Engine-ML_ has specific hardware instructions for matrix multiplications. Depending on the bitwidth of the operands, various matrix sizes are supported. In the following table the notation `MxKxN` means that matrix multiplication with a first operand of size M rows x K columns and a second operand of size K rows x N columns is supported.
The *AI Engine-ML* has specific hardware instructions for matrix multiplications. Depending on the bitwidth of the operands, various matrix sizes are supported. In the following table the notation `MxKxN` means that matrix multiplication with a first operand of size M rows x K columns and a second operand of size K rows x N columns is supported.

**Matrix Multiplication modes for real types**

Expand Down Expand Up @@ -80,11 +80,11 @@ In order to avoid too many pointer manipulations, the **A** tiles will be read 2

This way to do offloads the pointer manipulation to the DMA programming, freeing some scalar processor cycles.

The next 2 animated GIFs will show how **A** matrix is read from the Memory Tile and how **C** matrix is written to it. You can see that I chose to have __super tiles__ consisting of 2 sub-matrices one above the other:
The next 2 animated GIFs will show how **A** matrix is read from the Memory Tile and how **C** matrix is written to it. You can see that I chose to have **super tiles** consisting of 2 sub-matrices one above the other:

![Matrix **A** read order](images/OptA_Order.gif)
![Matrix A read order](images/OptA_Order.gif)

![Matrix **C** write order](images/OptC_Order.gif)
![Matrix C write order](images/OptC_Order.gif)

These read write orders are obtained using the following tiling parameters:

Expand Down Expand Up @@ -204,7 +204,7 @@ The 16-bit output version is doing a frog-leap in performances, **C** sub-matric

Let's have a look to this code:

![Inner Loop as seen in `vitis_analyzer`](images/InnerLoopOpt16bits.png)
![Inner Loop as seen in vitis_analyzer](images/InnerLoopOpt16bits.png)

Some lines (1568, 1584, ...) are not fully displayed in the interface, we need to get the original assembly code in the compilation directory (aie/Work1/aie/20_0/Release/20_0.lst). Let's focus on the inner loop delimited by the ZLS/ZLE flags (Zero Overhead Loop Start/End):

Expand Down
Original file line number Diff line number Diff line change
@@ -1,9 +1,8 @@
</table>
<table class="sphinxhide" width="100%">
<tr width="100%">
<td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>AI Engine Development</h1>
<td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>AIE-ML Development</h1>
<a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
<a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis™ AI Development Environment on xilinx.com</a>
<a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis™ AI Development Environment on xilinx.com</br></a>
</td>
</tr>
</table>
Expand Down
Loading

0 comments on commit 99ee264

Please sign in to comment.