Common IP cores intended for internal use in projects under Sigma Logic organization. Mainly targeting Gowin Arora V FPGA chips family, but not exclusively.
You are free to use IP cores with no limitations in personal projects or by including this git repository as a submodule in your project. If you copy, edit, modify or indirectly adding contents (hdl code) of the IP cores in a public project, please mention original repository link and the author (repo owner) in comments inside hdl code or readme.md file. Do not use in commertial projects.
| Name | Description | Dev Status | Notes |
|---|---|---|---|
| WS2812 | Addressable RGB led driver | New (unstable) | Supports only single LED |
| RGMII | RGMII phy level | WiP (unstable) | Network stack up to you, it's only DDR buffer |
| Simple PLL | PLL configuration covering most needs | Stable | Just cozy PLL module |
| LVDS | LVDS I/O buffers | Stable | Wrapper around ELVDS/TLVDS |