Merge pull request #80 from siliconcompiler/fix-again

fix verilog syntax error
siliconcompiler · Aug 29, 2024 · be69126 · be69126
2 parents 6cd36a4 + 288dc3a
commit be69126
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Showing 3 changed files with 13 additions and 13 deletions.
diff --git a/lambdapdk/__init__.py b/lambdapdk/__init__.py
@@ -1,7 +1,7 @@
 import siliconcompiler.package as sc_package
 
 
-__version__ = "0.1.30"
+__version__ = "0.1.31"
 
 
 def register_data_source(chip):

diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_iopoc.v b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_iopoc.v
@@ -4,12 +4,12 @@ module la_iopoc #(
     parameter CFGW  = 16,         // width of core config bus
     parameter RINGW = 8           // width of io ring
 ) (
-    inout             vdd,    // core supply
-    inout             vss,    // core ground
-    inout             vddio,  // io supply
-    inout             vssio,  // io ground
-    inout [RINGW-1:0] ioring  // generic io-ring interface
-    input [ CFGW-1:0] cfg     // generic config interface
+    inout             vdd,     // core supply
+    inout             vss,     // core ground
+    inout             vddio,   // io supply
+    inout             vssio,   // io ground
+    inout [RINGW-1:0] ioring,  // generic io-ring interface
+    input [ CFGW-1:0] cfg      // generic config interface
 );
 
 endmodule
diff --git a/lambdapdk/sky130/libs/sky130io/lambda/la_iopoc.v b/lambdapdk/sky130/libs/sky130io/lambda/la_iopoc.v
@@ -4,12 +4,12 @@ module la_iopoc #(
     parameter CFGW  = 16,         // width of core config bus
     parameter RINGW = 8           // width of io ring
 ) (
-    inout             vdd,    // core supply
-    inout             vss,    // core ground
-    inout             vddio,  // io supply
-    inout             vssio,  // io ground
-    inout [RINGW-1:0] ioring  // generic io-ring interface
-    input [ CFGW-1:0] cfg     // generic config interface
+    inout             vdd,     // core supply
+    inout             vss,     // core ground
+    inout             vddio,   // io supply
+    inout             vssio,   // io ground
+    inout [RINGW-1:0] ioring,  // generic io-ring interface
+    input [ CFGW-1:0] cfg      // generic config interface
 );
 
 endmodule