refactor: maintenance after merge

slothy-optimizer · Jan 15, 2025 · e448909 · e448909
1 parent 30cce36
commit e448909
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Showing 2 changed files with 40 additions and 1 deletion.
diff --git a/example.py b/example.py
@@ -645,6 +645,22 @@ def core(self,slothy):
         slothy.config.sw_pipelining.optimize_postamble = False
         slothy.optimize_loop("start")
 
+class AArch64Split0(Example):
+    def __init__(self, var="", arch=AArch64_Neon, target=Target_CortexA55):
+        name = "aarch64_split0"
+        infile = name
+
+        if var != "":
+            name += f"_{var}"
+            infile += f"_{var}"
+        name += f"_{target_label_dict[target]}"
+
+        super().__init__(infile, name, rename=True, arch=arch, target=target)
+
+    def core(self,slothy):
+        slothy.config.allow_useless_instructions = True
+        slothy.fusion_region("start", "end", ssa=False)
+
 class Armv7mExample0(Example):
     def __init__(self, var="", arch=Arch_Armv7M, target=Target_CortexM7):
         name = "armv7m_simple0"
@@ -662,6 +678,24 @@ def core(self,slothy):
         slothy.config.inputs_are_outputs = True
         slothy.optimize(start="start", end="end")
 
+class Armv7mExample0Func(Example):
+    def __init__(self, var="", arch=Arch_Armv7M, target=Target_CortexM7):
+        name = "armv7m_simple0_func"
+        infile = name
+
+        if var != "":
+            name += f"_{var}"
+            infile += f"_{var}"
+        name += f"_{target_label_dict[target]}"
+
+        super().__init__(infile, name, rename=True, arch=arch, target=target)
+
+    def core(self,slothy):
+        slothy.config.variable_size=True
+        slothy.config.inputs_are_outputs = True
+        slothy.optimize(start="start", end="end")
+        slothy.global_selftest("my_func", {"r0": 1024 })
+
 class Armv7mLoopSubs(Example):
     def __init__(self, var="", arch=Arch_Armv7M, target=Target_CortexM7):
         name = "loop_subs"
@@ -2930,7 +2964,7 @@ def main():
                  RISC_VExample0(target=Target_XuanTieC908),
                  RISC_VExampleLoop0(),
                  RISC_V_ntt8l_singleissue_plant_rv64im(target=Target_XuanTieC908, timeout=300),
-                 RISC_V_poly_basemul_8l_acc_rv64im(target=Target_XuanTieC908)
+                 RISC_V_poly_basemul_8l_acc_rv64im(target=Target_XuanTieC908),
 
                  ntt_dilithium(),
                  intt_dilithium_123_456_78(),

diff --git a/slothy/targets/riscv/riscv.py b/slothy/targets/riscv/riscv.py
@@ -42,6 +42,11 @@
 
 llvm_mca_arch = "aarch64"
 
+llvm_mc_arch = None
+llvm_mc_attr = None
+unicorn_arch = None
+unicorn_mode = None
+
 
 class RegisterType(Enum):
     """