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Issue313 chiselgen vec chiselvecs #314

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val idx = trues.head._2
vals(idx).unbox
}
// else if (sels.exists{case Literal(true) => true; case _ => false}) {
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can you remind me what was wrong with this?

}
if (mem.writers.isEmpty) {emit(src"val w0 = AccessHelper.singular(32)")}
if (mem.writers.isEmpty) {emit(src"lazy val w0 = AccessHelper.singular(32)")}
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what is the advantage of making these lazy vals?

warn(s"Detected potential write conflicts on ${a.access.ctx} (uid: ${a.unroll}) and ${conflicts.head.access.ctx} (uid: ${conflicts.head.unroll}) to memory ${mem.ctx} (${mem.name.getOrElse("")})")
warn(s" These are technically unbankable but you signed the waiver (by adding .conflictable) that says you know what you are doing")
// warn(s"Detected potential write conflicts on ${a.access.ctx} (uid: ${a.unroll}) and ${conflicts.head.access.ctx} (uid: ${conflicts.head.unroll}) to memory ${mem.ctx} (${mem.name.getOrElse("")})")
// warn(s" These are technically unbankable but you signed the waiver (by adding .conflictable) that says you know what you are doing")
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were these warns removed on purpose?

@@ -451,7 +451,7 @@ object modeling {
val readsAfter = parentScope.drop(writePosition).collect{case x if (x.isReader && paths.contains(x) && paths.contains(regWrite) && paths(x).toInt <= paths(regWrite).toInt && x.readMem.isDefined && x.readMem.get == reg && !reg.hotSwapPairings.getOrElse(x,Set()).contains(regWrite)) => x}
readsAfter.foreach{r =>
val dist = paths(regWrite).toInt - paths(r).toInt
warn(s"Avoid reading register (${reg.name.getOrElse("??")}) after writing to it in the same inner loop, if this is not an accumulation (write: ${regWrite.ctx}, read: ${r.ctx})")
// warn(s"Avoid reading register (${reg.name.getOrElse("??")}) after writing to it in the same inner loop, if this is not an accumulation (write: ${regWrite.ctx}, read: ${r.ctx})")
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removed temporarily to prevent spam?

assert(getArg(z0) == 3)
assert(getArg(z1) == 5)
}
}
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this test is already in VecTypes.scala in master so this file can be dropped

val otherUInt: UInt = other.asUInt
vec := otherUInt.asTypeOf(vec)
}
}
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@mattfel1 mattfel1 Oct 31, 2020

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If I understand correctly, this means we can change my recent update for vecs in structs:

    case FieldApply(struct, field) =>
      emit(createWire(quote(lhs),remap(lhs.tp)))
      val (start, end) = getField(struct.tp, field)
      lhs.tp match {
        case v: Vec[_] => emit(src"$lhs.toSeq.zipWithIndex.foreach{case (fa, i) => fa := $struct($start, $end + (${v.size - 1} - i) * ${bitWidth(v.typeArgs.head)})}")
        case _ => emit(src"$lhs.r := $struct($start, $end)")
      }

to just $lhs := $struct($start, $end) for the case of a Vec field?

Or is this UIntlike trait used in a different way somewhere that I missed?

# Conflicts:
#	fringe/src/fringe/utils/implicits.scala
…s' into issue313_chiselgen_vec_chiselvecs

# Conflicts:
#	test/spatial/tests/compiler/VecInStruct.scala
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