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Use set instead of bits
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@usbalbin
usbalbin committed Dec 17, 2024
1 parent cf5a479 commit d230335
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Showing 24 changed files with 230 additions and 325 deletions.
4 changes: 1 addition & 3 deletions examples/qspi_mdma.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -70,9 +70,7 @@ fn main() -> ! {
);
qspi.configure_mode(QspiMode::FourBit).unwrap();
// Disable address phase
qspi.inner_mut()
.ccr()
.modify(|_, w| unsafe { w.admode().bits(0) });
qspi.inner_mut().ccr().modify(|_, w| w.admode().set(0));

// Source buffer in TCM
let mut source_buffer: [u8; 80] = [0x4A; 80];
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64 changes: 28 additions & 36 deletions src/adc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -767,33 +767,31 @@ macro_rules! adc_hal {
fn set_chan_smp(&mut self, chan: u8) {
let t = self.get_sample_time().into();
if chan <= 9 {
//NOTE(unsafe) Only valid bit patterns written
self.rb.smpr1().modify(|_, w| unsafe { match chan {
0 => w.smp0().bits(t),
1 => w.smp1().bits(t),
2 => w.smp2().bits(t),
3 => w.smp3().bits(t),
4 => w.smp4().bits(t),
5 => w.smp5().bits(t),
6 => w.smp6().bits(t),
7 => w.smp7().bits(t),
8 => w.smp8().bits(t),
9 => w.smp9().bits(t),
self.rb.smpr1().modify(|_, w| { match chan {
0 => w.smp0().set(t),
1 => w.smp1().set(t),
2 => w.smp2().set(t),
3 => w.smp3().set(t),
4 => w.smp4().set(t),
5 => w.smp5().set(t),
6 => w.smp6().set(t),
7 => w.smp7().set(t),
8 => w.smp8().set(t),
9 => w.smp9().set(t),
_ => unreachable!(),
}});
} else {
//NOTE(unsafe) Only valid bit patterns written
self.rb.smpr2().modify(|_, w| unsafe { match chan {
10 => w.smp10().bits(t),
11 => w.smp11().bits(t),
12 => w.smp12().bits(t),
13 => w.smp13().bits(t),
14 => w.smp14().bits(t),
15 => w.smp15().bits(t),
16 => w.smp16().bits(t),
17 => w.smp17().bits(t),
18 => w.smp18().bits(t),
19 => w.smp19().bits(t),
self.rb.smpr2().modify(|_, w| { match chan {
10 => w.smp10().set(t),
11 => w.smp11().set(t),
12 => w.smp12().set(t),
13 => w.smp13().set(t),
14 => w.smp14().set(t),
15 => w.smp15().set(t),
16 => w.smp16().set(t),
17 => w.smp17().set(t),
18 => w.smp18().set(t),
19 => w.smp19().set(t),
_ => unreachable!(),
}});
}
Expand All @@ -805,16 +803,14 @@ macro_rules! adc_hal {

// Set LSHIFT[3:0]
//NOTE(unsafe) Only valid bit patterns written
unsafe {
self.rb.cfgr2().modify(|_, w| w.lshift().bits(self.get_lshift().value()));
}
self.rb.cfgr2().modify(|_, w| w.lshift().set(self.get_lshift().value()));

// Select channel (with preselection, refer to RM0433 Rev 7 - Chapter 25.4.12)
self.rb.pcsel().modify(|r, w| unsafe { w.pcsel().bits(r.pcsel().bits() | (1 << chan)) });
self.set_chan_smp(chan);
self.rb.sqr1().modify(|_, w| unsafe {
w.sq1().bits(chan)
.l().bits(0)
.l().set(0)
});
self.current_channel = Some(chan);

Expand Down Expand Up @@ -854,14 +850,10 @@ macro_rules! adc_hal {
// Set resolution
self.rb.cfgr().modify(|_, w| unsafe { w.res().bits(self.get_resolution().into()) });


//NOTE(unsafe) Only valid bit patterns written
unsafe {
self.rb.cfgr().modify(|_, w| w.dmngt().bits(match mode {
AdcDmaMode::OneShot => 0b01,
AdcDmaMode::Circular => 0b11,
}));
}
self.rb.cfgr().modify(|_, w| w.dmngt().set(match mode {
AdcDmaMode::OneShot => 0b01,
AdcDmaMode::Circular => 0b11,
}));

// Set continuous mode
self.rb.cfgr().modify(|_, w| w.cont().set_bit().discen().clear_bit() );
Expand Down
29 changes: 9 additions & 20 deletions src/crc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -38,24 +38,18 @@ impl Crc {
// manual says unit must be reset (or DR read) before change of polynomial
// (technically only in case of ongoing calculation, but DR is buffered)
//NOTE(unsafe) Only valid bit patterns are written
self.reg.cr().modify(|_, w| unsafe {
self.reg.cr().modify(|_, w| {
w.polysize()
.bits(config.poly.polysize())
.set(config.poly.polysize())
.rev_in()
.bits(config.get_reverse_input())
.set(config.get_reverse_input())
.rev_out()
.bit(config.reverse_output)
.reset()
.set_bit()
});
//NOTE(unsafe) All bit patterns are valid
self.reg
.pol()
.write(|w| unsafe { w.pol().bits(config.poly.pol()) });
//NOTE(unsafe) All bit patterns are valid
self.reg
.init()
.write(|w| unsafe { w.init().bits(config.initial) });
self.reg.pol().write(|w| w.pol().set(config.poly.pol()));
self.reg.init().write(|w| w.init().set(config.initial));
// writing to INIT sets DR to its value
}

Expand All @@ -67,23 +61,18 @@ impl Crc {
let mut words = data.chunks_exact(4);
for word in words.by_ref() {
let word = u32::from_be_bytes(word.try_into().unwrap());
//NOTE(unsafe) All bit patterns are valid
self.reg.dr().write(|w| unsafe { w.dr().bits(word) });
self.reg.dr().write(|w| w.dr().set(word));
}

// there will be at most 3 bytes remaining, so 1 half-word and 1 byte
let mut half_word = words.remainder().chunks_exact(2);
if let Some(half_word) = half_word.next() {
let half_word = u16::from_be_bytes(half_word.try_into().unwrap());
//NOTE(unsafe) All bit patterns are valid
self.reg
.dr16()
.write(|w| unsafe { w.dr16().bits(half_word) });
self.reg.dr16().write(|w| w.dr16().set(half_word));
}

if let Some(byte) = half_word.remainder().first() {
//NOTE(unsafe) All bit patterns are valid
self.reg.dr8().write(|w| unsafe { w.dr8().bits(*byte) });
self.reg.dr8().write(|w| w.dr8().set(*byte));
}
}

Expand Down Expand Up @@ -136,7 +125,7 @@ impl Crc {
/// The IDR is not involved with CRC calculation.
pub fn set_idr(&mut self, value: u32) {
//NOTE(unsafe) All bit patterns are valid
self.reg.idr().write(|w| unsafe { w.idr().bits(value) });
self.reg.idr().write(|w| w.idr().set(value));
}

/// Get the current value of the independent data register.
Expand Down
4 changes: 2 additions & 2 deletions src/dma/bdma.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -357,7 +357,7 @@ where
unsafe {
Self::stream()
.cr()
.modify(|_, w| w.pl().bits(priority.bits()));
.modify(|_, w| w.pl().set(priority.bits()));
}
}

Expand Down Expand Up @@ -466,7 +466,7 @@ where
//NOTE(unsafe) We only access the registers that belongs to the StreamX
//NOTE(unsafe) All bit patterns are valid for ndt
unsafe {
Self::stream().ndtr().write(|w| w.ndt().bits(value));
Self::stream().ndtr().write(|w| w.ndt().set(value));
}
}
#[inline(always)]
Expand Down
10 changes: 5 additions & 5 deletions src/dma/dma.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -356,7 +356,7 @@ impl<I: Instance, const S: u8> StreamX<I, S> {
unsafe {
Self::stream()
.fcr()
.modify(|_, w| w.fth().bits(fifo_threshold.bits()));
.modify(|_, w| w.fth().set(fifo_threshold.bits()));
}
}

Expand All @@ -376,7 +376,7 @@ impl<I: Instance, const S: u8> StreamX<I, S> {
unsafe {
Self::stream()
.cr()
.modify(|_, w| w.mburst().bits(memory_burst.bits()));
.modify(|_, w| w.mburst().set(memory_burst.bits()));
}
}

Expand All @@ -387,7 +387,7 @@ impl<I: Instance, const S: u8> StreamX<I, S> {
unsafe {
Self::stream()
.cr()
.modify(|_, w| w.pburst().bits(peripheral_burst.bits()));
.modify(|_, w| w.pburst().set(peripheral_burst.bits()));
}
}

Expand Down Expand Up @@ -518,7 +518,7 @@ where
unsafe {
Self::stream()
.cr()
.modify(|_, w| w.pl().bits(priority.bits()));
.modify(|_, w| w.pl().set(priority.bits()));
}
}

Expand Down Expand Up @@ -645,7 +645,7 @@ where
//NOTE(unsafe) We only access the registers that belongs to the StreamX
//NOTE(unsafe) All bit pattern for ndt are valid
unsafe {
Self::stream().ndtr().write(|w| w.ndt().bits(value));
Self::stream().ndtr().write(|w| w.ndt().set(value));
}
}

Expand Down
24 changes: 11 additions & 13 deletions src/gpio.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -317,11 +317,9 @@ where
let offset = 2 * { N };

unsafe {
(*Gpio::<P>::ptr()).ospeedr().modify(|r, w| {
w.bits(
(r.bits() & !(0b11 << offset)) | ((speed as u32) << offset),
)
});
(*Gpio::<P>::ptr())
.ospeedr()
.modify(|_, w| w.ospeedr(offset).set(speed as u8));
}
}

Expand All @@ -339,11 +337,11 @@ where
/// Set the internal pull-up and pull-down resistor
pub fn set_internal_resistor(&mut self, resistor: Pull) {
let offset = 2 * { N };
let value = resistor as u32;
let value = resistor as u8;
unsafe {
(*Gpio::<P>::ptr()).pupdr().modify(|r, w| {
w.bits((r.bits() & !(0b11 << offset)) | (value << offset))
});
(*Gpio::<P>::ptr())
.pupdr()
.modify(|_, w| w.pupdr(offset).bits(value));
}
}

Expand Down Expand Up @@ -428,25 +426,25 @@ impl<const P: char, const N: u8, MODE> Pin<P, N, MODE> {
fn _set_high(&mut self) {
// NOTE(unsafe) atomic write to a stateless register
unsafe {
(*Gpio::<P>::ptr()).bsrr().write(|w| w.bits(1 << N));
(*Gpio::<P>::ptr()).bsrr().write(|w| w.bs(N).set_bit());
}
}
#[inline(always)]
fn _set_low(&mut self) {
// NOTE(unsafe) atomic write to a stateless register
unsafe {
(*Gpio::<P>::ptr()).bsrr().write(|w| w.bits(1 << (16 + N)));
(*Gpio::<P>::ptr()).bsrr().write(|w| w.br(N).set_bit());
}
}
#[inline(always)]
fn _is_set_low(&self) -> bool {
// NOTE(unsafe) atomic read with no side effects
unsafe { (*Gpio::<P>::ptr()).odr().read().bits() & (1 << N) == 0 }
unsafe { (*Gpio::<P>::ptr()).odr().read().odr(N).is_low() }
}
#[inline(always)]
fn _is_low(&self) -> bool {
// NOTE(unsafe) atomic read with no side effects
unsafe { (*Gpio::<P>::ptr()).idr().read().bits() & (1 << N) == 0 }
unsafe { (*Gpio::<P>::ptr()).idr().read().idr(N).is_low() }
}
}

Expand Down
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