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1. synchronous-fifo synchronous-fifo Public

   Synchronous FIFO verilog code and testbench

   Verilog 7 3

2. trafficgen trafficgen Public

   AXI-4 stream traffic generator with configurable word size

   Verilog 6

3. asynchronous-fifo asynchronous-fifo Public

   Dual clock asynchronous FIFO with testbench

   VHDL 2 1

4. register-mode-dma register-mode-dma Public

   A register mode DMA example that demonstrates moving data from a traffic generator to DDR memory

   Verilog 2 3

5. finn finn Public

   Forked from Xilinx/finn

   Dataflow compiler for QNN inference on FPGAs

   Python

6. command-line-tutorial command-line-tutorial Public

   Forked from onyxfish/command-line-tutorial