wazevo: fuzz, fix Fcopysign

internal/engine/wazevo/backend/isa/arm64/lower_instr.go

@@ -1231,13 +1231,19 @@ func (m *machine) lowerFcopysignImpl(rd, rn, rm, tmpI, tmpF operand, _64bit bool
 	}
 	m.insert(setMSB)
 
+	tmpReg := operandNR(m.compiler.AllocateVReg(ssa.TypeF64))
+
 	mov := m.allocateInstr()
-	mov.asFpuMov64(rd.nr(), rn.nr())
+	mov.asFpuMov64(tmpReg.nr(), rn.nr())
 	m.insert(mov)
 
 	vbit := m.allocateInstr()
-	vbit.asVecRRR(vecOpBit, rd, rm, tmpF, vecArrangement8B)
+	vbit.asVecRRR(vecOpBit, tmpReg, rm, tmpF, vecArrangement8B)
 	m.insert(vbit)
+
+	movDst := m.allocateInstr()
+	movDst.asFpuMov64(rd.nr(), tmpReg.nr())
+	m.insert(movDst)
 }
 
 func (m *machine) lowerBitcast(instr *ssa.Instruction) {

internal/engine/wazevo/backend/isa/arm64/lower_instr_test.go

@@ -861,17 +861,19 @@ func TestMachine_lowerFcopysign(t *testing.T) {
 			exp: `
 movz w1?, #0x8000, lsl 16
 ins v2?.s[0], w1?
-mov v5?.8b, v3?.8b
-bit v5?.8b, v4?.8b, v2?.8b
+mov v6?.8b, v3?.8b
+bit v6?.8b, v4?.8b, v2?.8b
+mov v5?.8b, v6?.8b
 `,
 		},
 		{
 			_64bit: true,
 			exp: `
 movz x1?, #0x8000, lsl 48
 ins v2?.d[0], x1?
-mov v5?.8b, v3?.8b
-bit v5?.8b, v4?.8b, v2?.8b
+mov v6?.8b, v3?.8b
+bit v6?.8b, v4?.8b, v2?.8b
+mov v5?.8b, v6?.8b
 `,
 		},
 	} {

internal/integration_test/fuzzcases/fuzzcases_test.go

@@ -715,3 +715,19 @@ func Test1825(t *testing.T) {
 		require.Equal(t, uint64(18446744073709551615), m.Globals[6].ValHi)
 	})
 }
+
+// Test1825 tests that lowerFcopysignImpl allocates correctly the temporary registers.
+func Test1826(t *testing.T) {
+	if !platform.CompilerSupported() {
+		return
+	}
+	run(t, func(t *testing.T, r wazero.Runtime) {
+		mod, err := r.Instantiate(ctx, getWasmBinary(t, "1826"))
+		require.NoError(t, err)
+		m := mod.(*wasm.ModuleInstance)
+		_, err = m.ExportedFunction("3").Call(ctx, 0, 0)
+		require.NoError(t, err)
+		require.Equal(t, uint64(1608723901141126568), m.Globals[0].Val)
+		require.Equal(t, uint64(0), m.Globals[0].ValHi)
+	})
+}