refactor(core): streamline RAM layout

[no changelog]

core/SConscript.prodtest

@@ -136,7 +136,7 @@ env.Replace(
     '-fstack-protector-all '
     +  env.get('ENV')["CPU_CCFLAGS"] + CCFLAGS_MOD,
     CCFLAGS_QSTR='-DNO_QSTR -DN_X64 -DN_X86 -DN_THUMB',
-    LINKFLAGS=f'-T build/prodtest/memory.ld -Wl,--gc-sections -Wl,-Map=build/prodtest/prodtest.map -Wl,--warn-common',
+    LINKFLAGS=f'-T build/prodtest/memory.ld -Wl,--gc-sections -Wl,--print-memory-usage -Wl,-Map=build/prodtest/prodtest.map -Wl,--warn-common',
     CPPPATH=[
         'embed/projects/prodtest',
         'embed/rtl/inc',

core/embed/models/D001/memory.ld

@@ -44,10 +44,25 @@ FIRMWARE_P2_START = 0x8120000;
 FIRMWARE_P2_MAXSIZE = 0xe0000;
 FIRMWARE_P2_SECTOR_START = 0x11;
 FIRMWARE_P2_SECTOR_END = 0x17;
-KERNEL_STACK_SIZE = 0x2000;
-KERNEL_CCMRAM_SIZE = 0x4000;
-KERNEL_FRAMEBUFFER_SIZE = 0x0;
-KERNEL_SRAM_SIZE = 0x400;
+S_MAIN_STACK_START = 0x10000000;
+S_MAIN_STACK_SIZE = 0x4000;
+S_FB1_RAM_START = 0x10004000;
+S_FB1_RAM_SIZE = 0x0;
+S_MAIN_RAM_START = 0x10004000;
+S_MAIN_RAM_SIZE = 0xbf00;
+K_MAIN_STACK_START = 0x10000000;
+K_MAIN_STACK_SIZE = 0x2000;
+K_AUX2_RAM_START = 0x10002000;
+K_AUX2_RAM_SIZE = 0xa000;
+K_FB1_RAM_START = 0x1000c000;
+K_FB1_RAM_SIZE = 0x0;
+K_MAIN_RAM_START = 0x1000c000;
+K_MAIN_RAM_SIZE = 0x3f00;
+BOOTARGS_START = 0x1000ff00;
 BOOTARGS_SIZE = 0x100;
+DMABUF_RAM_START = 0x20000000;
+DMABUF_RAM_SIZE = 0x400;
+AUX1_RAM_START = 0x20000400;
+AUX1_RAM_SIZE = 0x2fc00;
 CODE_ALIGNMENT = 0x200;
 COREAPP_ALIGNMENT = 0x200;

core/embed/models/D001/model_D001.h

@@ -89,13 +89,40 @@
 #define FIRMWARE_P2_SECTOR_START 17
 #define FIRMWARE_P2_SECTOR_END 23
 
-// RAM layout
-#define KERNEL_STACK_SIZE (8 * 1024)
-#define KERNEL_CCMRAM_SIZE (16 * 1024)
-#define KERNEL_FRAMEBUFFER_SIZE (0 * 1024)
-#define KERNEL_SRAM_SIZE (1 * 1024)
+// Ram layout - shared boardloader, bootloader, prodtest
+#define S_MAIN_STACK_START 0x10000000
+#define S_MAIN_STACK_SIZE (16 * 1024)
 
+#define S_FB1_RAM_START 0x10004000
+#define S_FB1_RAM_SIZE (0)
+
+#define S_MAIN_RAM_START 0x10004000
+#define S_MAIN_RAM_SIZE (48 * 1024 - 0x100)
+
+// RAM layout - kernel
+#define K_MAIN_STACK_START 0x10000000
+#define K_MAIN_STACK_SIZE (8 * 1024)
+
+#define K_AUX2_RAM_START 0x10002000
+#define K_AUX2_RAM_SIZE (40 * 1024)
+
+#define K_FB1_RAM_START 0x1000C000
+#define K_FB1_RAM_SIZE (0)
+
+#define K_MAIN_RAM_START 0x1000C000
+#define K_MAIN_RAM_SIZE (16 * 1024 - 0x100)
+
+// RAM layout - common
+#define BOOTARGS_START 0x1000FF00
 #define BOOTARGS_SIZE 0x100
+
+#define DMABUF_RAM_START 0x20000000
+#define DMABUF_RAM_SIZE (1 * 1024)
+
+#define AUX1_RAM_START (0x20000400)
+#define AUX1_RAM_SIZE (191 * 1024)
+
+// misc
 #define CODE_ALIGNMENT 0x200
 #define COREAPP_ALIGNMENT 0x200
 

core/embed/models/D002/memory.ld

@@ -39,8 +39,17 @@ ASSETS_START = 0xc3f0000;
 ASSETS_MAXSIZE = 0x10000;
 ASSETS_SECTOR_START = 0x1f8;
 ASSETS_SECTOR_END = 0x1ff;
-KERNEL_U_RAM_SIZE = 0x200;
-KERNEL_SRAM2_SIZE = 0xfe00;
-BOOTARGS_SIZE = 0x100;
+FB1_RAM_START = 0x30000000;
+FB1_RAM_SIZE = 0xbfe00;
+BOOTARGS_START = 0x300bfe00;
+BOOTARGS_SIZE = 0x200;
+MAIN_RAM_START = 0x300c0000;
+MAIN_RAM_SIZE = 0xfe00;
+SAES_RAM_START = 0x300cfe00;
+SAES_RAM_SIZE = 0x200;
+FB2_RAM_START = 0x300d0000;
+FB2_RAM_SIZE = 0xc0000;
+AUX1_RAM_START = 0x30190000;
+AUX1_RAM_SIZE = 0xe0000;
 CODE_ALIGNMENT = 0x400;
 COREAPP_ALIGNMENT = 0x2000;

core/embed/models/D002/model_D002.h

@@ -85,10 +85,25 @@
 #define ASSETS_SECTOR_END 0x1FF
 
 // RAM layout
-#define KERNEL_U_RAM_SIZE 512
-#define KERNEL_SRAM2_SIZE (64 * 1024 - 512)
+#define FB1_RAM_START 0x30000000
+#define FB1_RAM_SIZE (768 * 1024 - 512)
 
-#define BOOTARGS_SIZE 0x100
+#define BOOTARGS_START 0x300BFE00
+#define BOOTARGS_SIZE 0x200
+
+#define MAIN_RAM_START 0x300C0000
+#define MAIN_RAM_SIZE (64 * 1024 - 512)
+
+#define SAES_RAM_START 0x300CFE00
+#define SAES_RAM_SIZE 512
+
+#define FB2_RAM_START 0x300D0000
+#define FB2_RAM_SIZE (768 * 1024)
+
+#define AUX1_RAM_START 0x30190000
+#define AUX1_RAM_SIZE (896 * 1024)
+
+// misc
 #define CODE_ALIGNMENT 0x400
 #define COREAPP_ALIGNMENT 0x2000
 

core/embed/models/T2B1/memory.ld

@@ -48,10 +48,25 @@ FIRMWARE_P2_START = 0x8120000;
 FIRMWARE_P2_MAXSIZE = 0xe0000;
 FIRMWARE_P2_SECTOR_START = 0x11;
 FIRMWARE_P2_SECTOR_END = 0x17;
-KERNEL_STACK_SIZE = 0x2000;
-KERNEL_CCMRAM_SIZE = 0x4000;
-KERNEL_FRAMEBUFFER_SIZE = 0x2000;
-KERNEL_SRAM_SIZE = 0x400;
+S_MAIN_STACK_START = 0x10000000;
+S_MAIN_STACK_SIZE = 0x4000;
+S_FB1_RAM_START = 0x10004000;
+S_FB1_RAM_SIZE = 0x2000;
+S_MAIN_RAM_START = 0x10006000;
+S_MAIN_RAM_SIZE = 0x9f00;
+K_MAIN_STACK_START = 0x10000000;
+K_MAIN_STACK_SIZE = 0x2000;
+K_AUX2_RAM_START = 0x10002000;
+K_AUX2_RAM_SIZE = 0x8000;
+K_FB1_RAM_START = 0x1000a000;
+K_FB1_RAM_SIZE = 0x2000;
+K_MAIN_RAM_START = 0x1000c000;
+K_MAIN_RAM_SIZE = 0x3f00;
+BOOTARGS_START = 0x1000ff00;
 BOOTARGS_SIZE = 0x100;
+DMABUF_RAM_START = 0x20000000;
+DMABUF_RAM_SIZE = 0x400;
+AUX1_RAM_START = 0x20000400;
+AUX1_RAM_SIZE = 0x2fc00;
 CODE_ALIGNMENT = 0x200;
 COREAPP_ALIGNMENT = 0x200;

core/embed/models/T2B1/model_T2B1.h

@@ -94,13 +94,40 @@
 #define FIRMWARE_P2_SECTOR_START 17
 #define FIRMWARE_P2_SECTOR_END 23
 
-// RAM layout
-#define KERNEL_STACK_SIZE (8 * 1024)
-#define KERNEL_CCMRAM_SIZE (16 * 1024)
-#define KERNEL_FRAMEBUFFER_SIZE (8 * 1024)
-#define KERNEL_SRAM_SIZE (1 * 1024)
+// Ram layout - shared boardloader, bootloader, prodtest
+#define S_MAIN_STACK_START 0x10000000
+#define S_MAIN_STACK_SIZE (16 * 1024)
 
+#define S_FB1_RAM_START 0x10004000
+#define S_FB1_RAM_SIZE (8 * 1024)
+
+#define S_MAIN_RAM_START 0x10006000
+#define S_MAIN_RAM_SIZE (40 * 1024 - 0x100)
+
+// RAM layout - kernel
+#define K_MAIN_STACK_START 0x10000000
+#define K_MAIN_STACK_SIZE (8 * 1024)
+
+#define K_AUX2_RAM_START 0x10002000
+#define K_AUX2_RAM_SIZE (32 * 1024)
+
+#define K_FB1_RAM_START 0x1000A000
+#define K_FB1_RAM_SIZE (8 * 1024)
+
+#define K_MAIN_RAM_START 0x1000C000
+#define K_MAIN_RAM_SIZE (16 * 1024 - 0x100)
+
+// RAM layout - common
+#define BOOTARGS_START 0x1000FF00
 #define BOOTARGS_SIZE 0x100
+
+#define DMABUF_RAM_START 0x20000000
+#define DMABUF_RAM_SIZE (1 * 1024)
+
+#define AUX1_RAM_START (0x20000400)
+#define AUX1_RAM_SIZE (191 * 1024)
+
+// misc
 #define CODE_ALIGNMENT 0x200
 #define COREAPP_ALIGNMENT 0x200
 

core/embed/models/T2T1/memory.ld

@@ -44,10 +44,25 @@ FIRMWARE_P2_START = 0x8120000;
 FIRMWARE_P2_MAXSIZE = 0xe0000;
 FIRMWARE_P2_SECTOR_START = 0x11;
 FIRMWARE_P2_SECTOR_END = 0x17;
-KERNEL_STACK_SIZE = 0x2000;
-KERNEL_CCMRAM_SIZE = 0x4000;
-KERNEL_FRAMEBUFFER_SIZE = 0x0;
-KERNEL_SRAM_SIZE = 0x400;
+S_MAIN_STACK_START = 0x10000000;
+S_MAIN_STACK_SIZE = 0x4000;
+S_FB1_RAM_START = 0x10004000;
+S_FB1_RAM_SIZE = 0x0;
+S_MAIN_RAM_START = 0x10004000;
+S_MAIN_RAM_SIZE = 0xbf00;
+K_MAIN_STACK_START = 0x10000000;
+K_MAIN_STACK_SIZE = 0x2000;
+K_AUX2_RAM_START = 0x10002000;
+K_AUX2_RAM_SIZE = 0xa000;
+K_FB1_RAM_START = 0x1000c000;
+K_FB1_RAM_SIZE = 0x0;
+K_MAIN_RAM_START = 0x1000c000;
+K_MAIN_RAM_SIZE = 0x3f00;
+BOOTARGS_START = 0x1000ff00;
 BOOTARGS_SIZE = 0x100;
+DMABUF_RAM_START = 0x20000000;
+DMABUF_RAM_SIZE = 0x400;
+AUX1_RAM_START = 0x20000400;
+AUX1_RAM_SIZE = 0x2fc00;
 CODE_ALIGNMENT = 0x200;
 COREAPP_ALIGNMENT = 0x200;

core/embed/models/T2T1/model_T2T1.h

@@ -89,13 +89,40 @@
 #define FIRMWARE_P2_SECTOR_START 17
 #define FIRMWARE_P2_SECTOR_END 23
 
-// RAM layout
-#define KERNEL_STACK_SIZE (8 * 1024)
-#define KERNEL_CCMRAM_SIZE (16 * 1024)
-#define KERNEL_FRAMEBUFFER_SIZE (0 * 1024)
-#define KERNEL_SRAM_SIZE (1 * 1024)
+// Ram layout - shared boardloader, bootloader, prodtest
+#define S_MAIN_STACK_START 0x10000000
+#define S_MAIN_STACK_SIZE (16 * 1024)
 
+#define S_FB1_RAM_START 0x10004000
+#define S_FB1_RAM_SIZE (0)
+
+#define S_MAIN_RAM_START 0x10004000
+#define S_MAIN_RAM_SIZE (48 * 1024 - 0x100)
+
+// RAM layout - kernel
+#define K_MAIN_STACK_START 0x10000000
+#define K_MAIN_STACK_SIZE (8 * 1024)
+
+#define K_AUX2_RAM_START 0x10002000
+#define K_AUX2_RAM_SIZE (40 * 1024)
+
+#define K_FB1_RAM_START 0x1000C000
+#define K_FB1_RAM_SIZE (0)
+
+#define K_MAIN_RAM_START 0x1000C000
+#define K_MAIN_RAM_SIZE (16 * 1024 - 0x100)
+
+// RAM layout - common
+#define BOOTARGS_START 0x1000FF00
 #define BOOTARGS_SIZE 0x100
+
+#define DMABUF_RAM_START 0x20000000
+#define DMABUF_RAM_SIZE (1 * 1024)
+
+#define AUX1_RAM_START (0x20000400)
+#define AUX1_RAM_SIZE (191 * 1024)
+
+// misc
 #define CODE_ALIGNMENT 0x200
 #define COREAPP_ALIGNMENT 0x200
 

core/embed/models/T3B1/memory.ld

@@ -38,9 +38,19 @@ ASSETS_START = 0xc1f0000;
 ASSETS_MAXSIZE = 0x10000;
 ASSETS_SECTOR_START = 0xf8;
 ASSETS_SECTOR_END = 0xff;
-KERNEL_U_RAM_SIZE = 0x200;
-KERNEL_SRAM2_SIZE = 0x6000;
-FRAMEBUFFER_SRAM_SIZE = 0x38400;
+AUX1_RAM_START = 0x30000000;
+AUX1_RAM_SIZE = 0x2fe00;
+BOOTARGS_START = 0x3002ff00;
 BOOTARGS_SIZE = 0x100;
+MAIN_RAM_START = 0x30030000;
+MAIN_RAM_SIZE = 0x5e00;
+SAES_RAM_START = 0x30035e00;
+SAES_RAM_SIZE = 0x200;
+AUX2_RAM_START = 0x30036000;
+AUX2_RAM_SIZE = 0x88000;
+FB1_RAM_START = 0x300be000;
+FB1_RAM_SIZE = 0x2000;
+FB2_RAM_START = 0x300c0000;
+FB2_RAM_SIZE = 0x0;
 CODE_ALIGNMENT = 0x200;
 COREAPP_ALIGNMENT = 0x2000;

core/embed/models/T3B1/model_T3B1.h

@@ -83,11 +83,30 @@
 #define ASSETS_SECTOR_END 0xFF
 
 // RAM layout
-#define KERNEL_U_RAM_SIZE 512
-#define KERNEL_SRAM2_SIZE (24 * 1024)
-#define FRAMEBUFFER_SRAM_SIZE 0x38400
+#define AUX1_RAM_START 0x30000000
+#define AUX1_RAM_SIZE (192 * 1024 - 512)
 
+// 256 bytes skipped - trustzone alignment vs fixed bootargs position
+
+#define BOOTARGS_START 0x3002FF00
 #define BOOTARGS_SIZE 0x100
+
+#define MAIN_RAM_START 0x30030000
+#define MAIN_RAM_SIZE (24 * 1024 - 512)
+
+#define SAES_RAM_START 0x30035E00
+#define SAES_RAM_SIZE 512
+
+#define AUX2_RAM_START 0x30036000
+#define AUX2_RAM_SIZE (544 * 1024)
+
+#define FB1_RAM_START 0x300BE000
+#define FB1_RAM_SIZE (0x2000)
+
+#define FB2_RAM_START 0x300C0000
+#define FB2_RAM_SIZE (0)
+
+// misc
 #define CODE_ALIGNMENT 0x200
 #define COREAPP_ALIGNMENT 0x2000
 

core/embed/models/T3T1/memory.ld

@@ -38,9 +38,19 @@ ASSETS_START = 0xc1f0000;
 ASSETS_MAXSIZE = 0x10000;
 ASSETS_SECTOR_START = 0xf8;
 ASSETS_SECTOR_END = 0xff;
-KERNEL_U_RAM_SIZE = 0x200;
-KERNEL_SRAM2_SIZE = 0x6000;
-FRAMEBUFFER_SRAM_SIZE = 0x38400;
+AUX1_RAM_START = 0x30000000;
+AUX1_RAM_SIZE = 0x2fe00;
+BOOTARGS_START = 0x3002ff00;
 BOOTARGS_SIZE = 0x100;
+MAIN_RAM_START = 0x30030000;
+MAIN_RAM_SIZE = 0x5e00;
+SAES_RAM_START = 0x30035e00;
+SAES_RAM_SIZE = 0x200;
+AUX2_RAM_START = 0x30036000;
+AUX2_RAM_SIZE = 0x51c00;
+FB1_RAM_START = 0x30087c00;
+FB1_RAM_SIZE = 0x1c200;
+FB2_RAM_START = 0x300a3e00;
+FB2_RAM_SIZE = 0x1c200;
 CODE_ALIGNMENT = 0x200;
 COREAPP_ALIGNMENT = 0x2000;