improve UART impl

us-irs · Sep 24, 2024 · 42e3cfd · 42e3cfd
1 parent a50f7a9
commit 42e3cfd
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Showing 5 changed files with 232 additions and 152 deletions.
diff --git a/examples/embassy/src/bin/uart-echo-with-irq.rs b/examples/embassy/src/bin/uart-echo-with-irq.rs
@@ -128,17 +128,14 @@ async fn blinky(mut led: Pin<PG5, OutputReadablePushPull>) {
 fn UART0_RX() {
     let mut buf: [u8; 16] = [0; 16];
     let mut read_len: usize = 0;
-    let mut irq_error = None;
+    let mut errors = None;
     RX.lock(|static_rx| {
         let mut rx_borrow = static_rx.borrow_mut();
         let rx_mut_ref = rx_borrow.as_mut().unwrap();
-        match rx_mut_ref.irq_handler(&mut buf) {
-            Ok(result) => {
-                read_len = result.bytes_read;
-            }
-            Err(e) => {
-                irq_error = Some(e);
-            }
+        let result = rx_mut_ref.irq_handler(&mut buf);
+        read_len = result.bytes_read;
+        if result.errors.is_some() {
+            errors = result.errors;
         }
     });
     let mut ringbuf_full = false;
@@ -155,8 +152,8 @@ fn UART0_RX() {
         });
     }
 
-    if irq_error.is_some() {
-        rprintln!("error in IRQ handler: {:?}", irq_error);
+    if errors.is_some() {
+        rprintln!("UART error: {:?}", errors);
     }
     if ringbuf_full {
         rprintln!("ringbuffer is full, deleted oldest data");

diff --git a/flashloader/src/main.rs b/flashloader/src/main.rs
@@ -293,8 +293,8 @@ mod app {
                         .read_fixed_len_or_timeout_based_using_irq(cx.local.rx_context)
                         .expect("read operation failed");
                 }
-                if result.error() {
-                    log::warn!("UART error: {:?}", result.error());
+                if result.has_errors() {
+                    log::warn!("UART error: {:?}", result.errors.unwrap());
                 }
             }
             Err(e) => {

diff --git a/va416xx-hal/CHANGELOG.md b/va416xx-hal/CHANGELOG.md
@@ -16,6 +16,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Added an additional way to read the UART RX with IRQs. The module documentation provides
   more information.
 - Made the UART with IRQ API more flexible for future additions.
+- Improved UART API result and error handling, added low level API to read from and write
+  to the FIFO directly
 
 ## Fixed
 

diff --git a/va416xx-hal/src/gpio/reg.rs b/va416xx-hal/src/gpio/reg.rs
@@ -113,14 +113,6 @@ pub(super) unsafe trait RegisterInterface {
     /// this type.
     fn id(&self) -> DynPinId;
 
-    const PORTA: *const PortRegisterBlock = Porta::ptr();
-    const PORTB: *const PortRegisterBlock = Portb::ptr();
-    const PORTC: *const PortRegisterBlock = Portc::ptr();
-    const PORTD: *const PortRegisterBlock = Portd::ptr();
-    const PORTE: *const PortRegisterBlock = Porte::ptr();
-    const PORTF: *const PortRegisterBlock = Portf::ptr();
-    const PORTG: *const PortRegisterBlock = Portg::ptr();
-
     /// Change the pin mode
     #[inline]
     fn change_mode(&mut self, mode: DynPinMode) {
@@ -155,13 +147,13 @@ pub(super) unsafe trait RegisterInterface {
     #[inline]
     fn port_reg(&self) -> &PortRegisterBlock {
         match self.id().group {
-            DynGroup::A => unsafe { &(*Self::PORTA) },
-            DynGroup::B => unsafe { &(*Self::PORTB) },
-            DynGroup::C => unsafe { &(*Self::PORTC) },
-            DynGroup::D => unsafe { &(*Self::PORTD) },
-            DynGroup::E => unsafe { &(*Self::PORTE) },
-            DynGroup::F => unsafe { &(*Self::PORTF) },
-            DynGroup::G => unsafe { &(*Self::PORTG) },
+            DynGroup::A => unsafe { &(*Porta::ptr()) },
+            DynGroup::B => unsafe { &(*Portb::ptr()) },
+            DynGroup::C => unsafe { &(*Portc::ptr()) },
+            DynGroup::D => unsafe { &(*Portd::ptr()) },
+            DynGroup::E => unsafe { &(*Porte::ptr()) },
+            DynGroup::F => unsafe { &(*Portf::ptr()) },
+            DynGroup::G => unsafe { &(*Portg::ptr()) },
         }
     }