Merge remote-tracking branch 'origin/master' into ganesh_dev

uwsampl · Jan 25, 2021 · 78e2a24 · 78e2a24
2 parents 70d0ecd + 658edb4
commit 78e2a24
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Showing 122 changed files with 303,927 additions and 26 deletions.
diff --git a/ARCH/fabric_key/fabric_key_32x32.xml b/ARCH/fabric_key/fabric_key_32x32.xml
diff --git a/...e/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/...e/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
diff --git a/...rch_template/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/...rch_template/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -216,7 +216,9 @@
     <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
   </direct_connection>
   <tile_annotations>
-    <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
+      <global_port name="clk" is_clock="true" default_val="0">
+          <tile name="clb" port="clk" x="-1" y="-1"/>
+      </global_port>
   </tile_annotations>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->

diff --git a/...mplate/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/...mplate/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -217,8 +217,12 @@
     <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
   </direct_connection>
   <tile_annotations>
-    <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
-    <global_port name="reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
+      <global_port name="clk" is_clock="true" default_val="0">
+          <tile name="clb" port="clk" x="-1" y="-1"/>
+      </global_port>
+      <global_port name="Reset" is_reset="true" default_val="1">
+          <tile name="clb" port="reset" x="-1" y="-1"/>
+      </global_port>
   </tile_annotations>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->

diff --git a/..._N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml b/..._N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
@@ -288,8 +288,12 @@
     <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
   </direct_connection>
   <tile_annotations>
-    <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
-    <global_port name="Reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
+      <global_port name="clk" is_clock="true" default_val="0">
+          <tile name="clb" port="clk" x="-1" y="-1"/>
+      </global_port>
+      <global_port name="Reset" is_reset="true" default_val="1">
+          <tile name="clb" port="reset" x="-1" y="-1"/>
+      </global_port>
   </tile_annotations>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->

diff --git a/...frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/...frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -229,8 +229,12 @@
     <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
   </direct_connection>
   <tile_annotations>
-    <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
-    <global_port name="Reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
+      <global_port name="clk" is_clock="true" default_val="0">
+          <tile name="clb" port="clk" x="-1" y="-1"/>
+      </global_port>
+      <global_port name="Reset" is_reset="true" default_val="1">
+          <tile name="clb" port="reset" x="-1" y="-1"/>
+      </global_port>
   </tile_annotations>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->

diff --git a/...te/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/...te/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -228,7 +228,9 @@
     <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
   </direct_connection>
   <tile_annotations>
-    <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
+      <global_port name="clk" is_clock="true" default_val="0">
+          <tile name="clb" port="clk" x="-1" y="-1"/>
+      </global_port>
   </tile_annotations>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->

diff --git a/ARCH/openfpga_arch_template/ql_ap3_8x8_arch_vpr_routing_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/ql_ap3_8x8_arch_vpr_routing_skywater130nm_fdhd_cc_openfpga.xml
@@ -214,7 +214,9 @@
     <direct name="adder_carry" circuit_model_name="direct_interc"/>
   </direct_connection>
   <tile_annotations>
-    <global_port name="clk" tile_port="SUPER_LOGIC_CELL.QCK" is_clock="true" default_val="0"/>
+      <global_port name="clk" is_clock="true" default_val="0">
+          <tile name="SUPER_LOGIC_CELL" port="QCK" x="-1" y="-1"/>
+      </global_port>
   </tile_annotations>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->