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Merge pull request lnis-uofu#107 from lnis-uofu/xt_dev
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Update timing annotation
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@tangxifan
tangxifan authored Apr 3, 2021
2 parents 2c0e779 + 004b5b7 commit 7c974f4
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8 changes: 4 additions & 4 deletions ...ac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
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Expand Up @@ -18,9 +18,9 @@ LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 2.31e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9
LUT4_DELAY: 2.6e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9
LUT3_DELAY: 0.86e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
LUT4_DELAY: 1.14e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
REGIN_TO_FF0_DELAY: 0.58e-9
FF0_TO_FF1_DELAY: 0.56e-9
8 changes: 4 additions & 4 deletions ...eset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -18,9 +18,9 @@ LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 2.31e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9
LUT4_DELAY: 2.6e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9
LUT3_DELAY: 0.92e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
LUT4_DELAY: 1.21e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
REGIN_TO_FF0_DELAY: 1.12e-9
FF0_TO_FF1_DELAY: 0.56e-9
11 changes: 8 additions & 3 deletions DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg
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28 changes: 14 additions & 14 deletions DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst
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Expand Up @@ -8,12 +8,12 @@ Timing Annotation
Configurable Logic Block
^^^^^^^^^^^^^^^^^^^^^^^^

The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`.
The path delays in :numref:`fig_qlsofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`.

.. _fig_qlsofa_hd_fle_arch_timing:

.. figure:: ./figures/qlsofa_hd_fle_arch_timing.svg
:scale: 30%
:width: 80%
:alt: Schematic of a logic element used in QLSOFA HD FPGA

Schematic of a logic element used in QLSOFA HD FPGA
Expand All @@ -25,25 +25,27 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| in0 -> LUT3_out[0] [1]_ | 2.31 |
| in0 -> LUT3_out[0] | 0.85 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[0] [1]_ | 2.31 |
| in1 -> LUT3_out[0] | 0.57 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[0] [1]_ | 2.31 |
| in2 -> B | 0.60 |
+-------------------------+------------------------------+
| in0 -> LUT3_out[1] [1]_ | 2.31 |
| B -> LUT3_out[0] | 0.32 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[1] [1]_ | 2.31 |
| in0 -> LUT3_out[1] | 0.90 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[1] [1]_ | 2.31 |
| in1 -> LUT3_out[1] | 0.62 |
+-------------------------+------------------------------+
| in0 -> LUT4_out [1]_ | 2.60 |
| B -> LUT3_out[1] | 0.33 |
+-------------------------+------------------------------+
| in1 -> LUT4_out [1]_ | 2.60 |
| in0 -> LUT4_out | 1.17 |
+-------------------------+------------------------------+
| in2 -> LUT4_out [1]_ | 2.60 |
| in1 -> LUT4_out | 0.89 |
+-------------------------+------------------------------+
| in3 -> LUT4_out [1]_ | 2.60 |
| in2 -> LUT4_out | 1.21 |
+-------------------------+------------------------------+
| in3 -> LUT4_out | 0.79 |
+-------------------------+------------------------------+
| LUT3_out[0] -> A | 0.56 |
+-------------------------+------------------------------+
Expand All @@ -66,8 +68,6 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
| FF[0] -> FF[1] | 0.56 |
+-------------------------+------------------------------+

.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques.
.. _qlsofa_hd_timing_io:

I/O Block
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11 changes: 8 additions & 3 deletions DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg
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25 changes: 13 additions & 12 deletions DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst
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Expand Up @@ -13,7 +13,7 @@ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref:
.. _fig_sofa_chd_fle_arch_timing:

.. figure:: ./figures/sofa_chd_fle_arch_timing.svg
:scale: 30%
:width: 80%
:alt: Schematic of a logic element used in SOFA CHD FPGA

Schematic of a logic element used in SOFA CHD FPGA
Expand All @@ -25,25 +25,27 @@ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref:
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| in0 -> LUT3_out[0] [1]_ | 2.31 |
| in0 -> LUT3_out[0] | 0.85 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[0] [1]_ | 2.31 |
| in1 -> LUT3_out[0] | 0.57 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[0] [1]_ | 2.31 |
| in2 -> B | 0.60 |
+-------------------------+------------------------------+
| in0 -> LUT3_out[1] [1]_ | 2.31 |
| B -> LUT3_out[0] | 0.32 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[1] [1]_ | 2.31 |
| in0 -> LUT3_out[1] | 0.90 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[1] [1]_ | 2.31 |
| in1 -> LUT3_out[1] | 0.62 |
+-------------------------+------------------------------+
| in0 -> LUT4_out [1]_ | 2.60 |
| B -> LUT3_out[1] | 0.33 |
+-------------------------+------------------------------+
| in1 -> LUT4_out [1]_ | 2.60 |
| in0 -> LUT4_out | 1.17 |
+-------------------------+------------------------------+
| in2 -> LUT4_out [1]_ | 2.60 |
| in1 -> LUT4_out | 0.89 |
+-------------------------+------------------------------+
| in3 -> LUT4_out [1]_ | 2.60 |
| in2 -> LUT4_out | 1.21 |
+-------------------------+------------------------------+
| in3 -> LUT4_out | 0.79 |
+-------------------------+------------------------------+
| LUT3_out[0] -> A | 0.56 |
+-------------------------+------------------------------+
Expand All @@ -66,7 +68,6 @@ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref:
| FF[0] -> FF[1] | 0.56 |
+-------------------------+------------------------------+

.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques.

.. _sofa_chd_timing_io:

Expand Down
24 changes: 11 additions & 13 deletions DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
.. _fig_sofa_hd_fle_arch_timing:

.. figure:: ./figures/sofa_hd_fle_arch_timing.svg
:scale: 30%
:width: 80%
:alt: Schematic of a logic element used in SOFA HD FPGA

Schematic of a logic element used in SOFA HD FPGA
Expand All @@ -25,25 +25,25 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| in0 -> LUT3_out[0] [1]_ | 2.31 |
| in0 -> LUT3_out[0] | 0.85 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[0] [1]_ | 2.31 |
| in1 -> LUT3_out[0] | 0.57 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[0] [1]_ | 2.31 |
| in2 -> LUT3_out[0] | 0.30 |
+-------------------------+------------------------------+
| in0 -> LUT3_out[1] [1]_ | 2.31 |
| in0 -> LUT3_out[1] | 0.86 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[1] [1]_ | 2.31 |
| in1 -> LUT3_out[1] | 0.59 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[1] [1]_ | 2.31 |
| in2 -> LUT3_out[1] | 0.31 |
+-------------------------+------------------------------+
| in0 -> LUT4_out [1]_ | 2.60 |
| in0 -> LUT4_out | 1.14 |
+-------------------------+------------------------------+
| in1 -> LUT4_out [1]_ | 2.60 |
| in1 -> LUT4_out | 0.86 |
+-------------------------+------------------------------+
| in2 -> LUT4_out [1]_ | 2.60 |
| in2 -> LUT4_out | 0.58 |
+-------------------------+------------------------------+
| in3 -> LUT4_out [1]_ | 2.60 |
| in3 -> LUT4_out | 0.51 |
+-------------------------+------------------------------+
| LUT3_out[0] -> A | 0.56 |
+-------------------------+------------------------------+
Expand All @@ -66,8 +66,6 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
| FF[0] -> FF[1] | 0.56 |
+-------------------------+------------------------------+

.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques.
.. _sofa_hd_timing_io:

I/O Block
Expand Down
26 changes: 15 additions & 11 deletions SNPS_PT/SCRIPT/report_timing_cb.tcl
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Expand Up @@ -5,19 +5,23 @@
#
##################################
# Define environment variables
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";

#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
#
set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "QLSOFA_HD"
#set DEVICE_NAME "SOFA_CHD"

#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";

#set DEVICE_NAME "SOFA_HD"
set DEVICE_NAME "QLSOFA_HD"
#set DEVICE_NAME "SOFA_CHD"
if {"SOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
}

set TIMING_REPORT_HOME "../TIMING_REPORTS/";

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