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README.md: s/write_ilang/write_rtlil/
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It's my understanding write_ilang is deprecated so best no to mention it
in the README.
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povik committed Jul 10, 2023
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Expand Up @@ -156,9 +156,10 @@ reading and elaborating the design using the Verilog frontend:
yosys> read -sv tests/simple/fiedler-cooley.v
yosys> hierarchy -top up3down5

writing the design to the console in Yosys's internal format:
writing the design to the console in the RTLIL format used by Yosys
internally:

yosys> write_ilang
yosys> write_rtlil

convert processes (``always`` blocks) to netlist elements and perform
some simple optimizations:
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