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Toggle the RISC-V Vector Extension on and off #222

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merged 4 commits into from
Jan 22, 2025
+2,436 −2,427
Merged

Toggle the RISC-V Vector Extension on and off #222

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929ef1b
Remove unused EXTV code, clean up code, pragma once around vpu.h
MichaelJSr Jan 14, 2025
cb491dd
test
MichaelJSr Jan 14, 2025
a2cfeff
Added ifndef statements for the vector extension anywhere they didn't…
MichaelJSr Jan 14, 2025
6d27575
Revert some of "Added ifndef statements for the vector extension anyw…
MichaelJSr Jan 15, 2025
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4 changes: 2 additions & 2 deletions sim/simx/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -17,12 +17,12 @@ CXXFLAGS += $(CONFIGS)
LDFLAGS += $(THIRD_PARTY_DIR)/softfloat/build/Linux-x86_64-GCC/softfloat.a
LDFLAGS += -Wl,-rpath,$(THIRD_PARTY_DIR)/ramulator -L$(THIRD_PARTY_DIR)/ramulator -lramulator

SRCS = $(COMMON_DIR)/util.cpp $(COMMON_DIR)/mem.cpp $(COMMON_DIR)/softfloat_ext.cpp $(COMMON_DIR)/softfloat_ext.cpp $(COMMON_DIR)/rvfloats.cpp $(COMMON_DIR)/dram_sim.cpp
SRCS = $(COMMON_DIR)/util.cpp $(COMMON_DIR)/mem.cpp $(COMMON_DIR)/softfloat_ext.cpp $(COMMON_DIR)/rvfloats.cpp $(COMMON_DIR)/dram_sim.cpp
SRCS += $(SRC_DIR)/processor.cpp $(SRC_DIR)/cluster.cpp $(SRC_DIR)/socket.cpp $(SRC_DIR)/core.cpp $(SRC_DIR)/emulator.cpp $(SRC_DIR)/decode.cpp $(SRC_DIR)/execute.cpp $(SRC_DIR)/func_unit.cpp $(SRC_DIR)/cache_sim.cpp $(SRC_DIR)/mem_sim.cpp $(SRC_DIR)/local_mem.cpp $(SRC_DIR)/mem_coalescer.cpp $(SRC_DIR)/dcrs.cpp $(SRC_DIR)/types.cpp

# Add V extension sources
ifneq ($(findstring -DEXT_V_ENABLE, $(CONFIGS)),)
SRCS += $(SRC_DIR)/execute_v.cpp
SRCS += $(SRC_DIR)/vpu.cpp
endif

# Debugging
Expand Down
6 changes: 0 additions & 6 deletions sim/simx/arch.h
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Expand Up @@ -29,7 +29,6 @@ class Arch {
uint16_t num_cores_;
uint16_t num_clusters_;
uint16_t socket_size_;
uint16_t vsize_;
uint16_t num_barriers_;
uint64_t local_mem_base_;

Expand All @@ -40,7 +39,6 @@ class Arch {
, num_cores_(num_cores)
, num_clusters_(NUM_CLUSTERS)
, socket_size_(SOCKET_SIZE)
, vsize_(VLEN / 8)
, num_barriers_(NUM_BARRIERS)
, local_mem_base_(LMEM_BASE_ADDR)
{}
Expand Down Expand Up @@ -73,10 +71,6 @@ class Arch {
return socket_size_;
}

uint16_t vsize() const {
return vsize_;
}

};

}
2 changes: 2 additions & 0 deletions sim/simx/decode.cpp
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Expand Up @@ -453,6 +453,7 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
if (sep++ != 0) { os << ", "; } else { os << " "; }
os << "0x" << std::hex << instr.getImm() << std::dec;
}
#ifdef EXT_V_ENABLE
if (instr.getOpcode() == Opcode::SYS && instr.getFunc3() >= 5) {
// CSRs with immediate values
if (sep++ != 0) { os << ", "; } else { os << " "; }
Expand All @@ -462,6 +463,7 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
if (instr.getVattrMask() != 0) {
print_vec_attr(os, instr);
}
#endif
return os;
}
}
Expand Down
26 changes: 15 additions & 11 deletions sim/simx/emulator.cpp
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Expand Up @@ -33,7 +33,9 @@ using namespace vortex;
Emulator::warp_t::warp_t(const Arch& arch)
: ireg_file(arch.num_threads(), std::vector<Word>(MAX_NUM_REGS))
, freg_file(arch.num_threads(), std::vector<uint64_t>(MAX_NUM_REGS))
, vreg_file(MAX_NUM_REGS, std::vector<Byte>(arch.vsize()))
#ifdef EXT_V_ENABLE
, vreg_file(MAX_NUM_REGS, std::vector<Byte>(MAX_NUM_REGS))
#endif
, uuid(0)
{}

Expand All @@ -43,9 +45,11 @@ void Emulator::warp_t::clear(uint64_t startup_addr) {
this->uuid = 0;
this->fcsr = 0;

#ifdef EXT_V_ENABLE
this->vtype = {0, 0, 0, 0, 0};
this->vl = 0;
this->vlmax = 0;
#endif

for (auto& reg_file : this->ireg_file) {
for (auto& reg : reg_file) {
Expand All @@ -68,6 +72,7 @@ void Emulator::warp_t::clear(uint64_t startup_addr) {
}
}

#ifdef EXT_V_ENABLE
for (auto& reg_file : this->vreg_file) {
for (auto& reg : reg_file) {
#ifndef NDEBUG
Expand All @@ -77,16 +82,7 @@ void Emulator::warp_t::clear(uint64_t startup_addr) {
#endif
}
}

for (auto& reg_file : this->vreg_file) {
for (auto& reg : reg_file) {
#ifndef NDEBUG
reg = 0;
#else
reg = std::rand();
#endif
}
}
#endif
}

///////////////////////////////////////////////////////////////////////////////
Expand All @@ -102,13 +98,17 @@ Emulator::Emulator(const Arch &arch, const DCRS &dcrs, Core* core)
// considered to be big enough to hold input tiles for one output tile.
// In future versions, scratchpad size should be fixed to an appropriate value.
, scratchpad(std::vector<Word>(32 * 32 * 32768))
#ifdef EXT_V_ENABLE
, csrs_(arch.num_warps())
#endif
{
std::srand(50);

#ifdef EXT_V_ENABLE
for (uint32_t i = 0; i < arch_.num_warps(); ++i) {
csrs_.at(i).resize(arch.num_threads());
}
#endif

this->clear();
}
Expand Down Expand Up @@ -490,6 +490,7 @@ Word Emulator::get_csr(uint32_t addr, uint32_t tid, uint32_t wid) {
case VX_CSR_FRM: return (warps_.at(wid).fcsr >> 5);
case VX_CSR_FCSR: return warps_.at(wid).fcsr;

#ifdef EXT_V_ENABLE
// Vector CRSs
case VX_CSR_VSTART:
return csrs_.at(wid).at(tid)[VX_CSR_VSTART];
Expand All @@ -514,6 +515,7 @@ Word Emulator::get_csr(uint32_t addr, uint32_t tid, uint32_t wid) {
return csrs_.at(wid).at(tid)[VX_CSR_VTIME];
case VX_CSR_VINSTRET:
return csrs_.at(wid).at(tid)[VX_CSR_VINSTRET];
#endif

case VX_CSR_MHARTID: return (core_->id() * arch_.num_warps() + wid) * arch_.num_threads() + tid;
case VX_CSR_THREAD_ID: return tid;
Expand Down Expand Up @@ -631,6 +633,7 @@ void Emulator::set_csr(uint32_t addr, Word value, uint32_t tid, uint32_t wid) {
csr_mscratch_ = value;
break;

#ifdef EXT_V_ENABLE
// Vector CRSs
case VX_CSR_VSTART:
csrs_.at(wid).at(tid)[VX_CSR_VSTART] = value;
Expand All @@ -652,6 +655,7 @@ void Emulator::set_csr(uint32_t addr, Word value, uint32_t tid, uint32_t wid) {
csrs_.at(wid).at(tid)[VX_CSR_VTYPE] = value;
break;
case VX_CSR_VLENB: // read only, set to VLEN / 8
#endif

case VX_CSR_SATP:
#ifdef VM_ENABLE
Expand Down
30 changes: 15 additions & 15 deletions sim/simx/execute.cpp
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Expand Up @@ -25,7 +25,9 @@
#include "emulator.h"
#include "instr.h"
#include "core.h"
#ifdef EXT_V_ENABLE
#include "processor_impl.h"
#endif
#include "VX_types.h"

using namespace vortex;
Expand Down Expand Up @@ -117,8 +119,10 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
}
DPN(2, "}" << std::endl);
break;
#ifdef EXT_V_ENABLE
case RegType::Vector:
break;
#endif
default:
break;
}
Expand Down Expand Up @@ -707,11 +711,12 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
}
}
rd_write = true;
} else {
#ifdef EXT_V_ENABLE
}
#ifdef EXT_V_ENABLE
else {
this->loadVector(instr, wid, rsdata);
#endif
}
#endif
break;
}
case Opcode::S:
Expand Down Expand Up @@ -744,11 +749,12 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
std::abort();
}
}
} else {
#ifdef EXT_V_ENABLE
}
#ifdef EXT_V_ENABLE
else {
this->storeVector(instr, wid, rsdata);
#endif
}
#endif
break;
}
case Opcode::AMO: {
Expand Down Expand Up @@ -932,7 +938,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
for (uint32_t t = thread_start; t < num_threads; ++t) {
if (!warp.tmask.test(t))
continue;
uint32_t frm = (func3 == 0x7) ? this->get_csr(VX_CSR_FRM, t, wid) : func3;
uint32_t frm = this->get_fpu_rm(func3, t, wid);
uint32_t fflags = 0;
switch (func7) {
case 0x00: { // RV32F: FADD.S
Expand Down Expand Up @@ -1247,10 +1253,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
break;
}
}
if (fflags) {
this->set_csr(VX_CSR_FCSR, this->get_csr(VX_CSR_FCSR, t, wid) | fflags, t, wid);
this->set_csr(VX_CSR_FFLAGS, this->get_csr(VX_CSR_FFLAGS, t, wid) | fflags, t, wid);
}
this->update_fcrs(fflags, t, wid);
}
rd_write = true;
break;
Expand Down Expand Up @@ -1304,10 +1307,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
default:
break;
}
if (fflags) {
this->set_csr(VX_CSR_FCSR, this->get_csr(VX_CSR_FCSR, t, wid) | fflags, t, wid);
this->set_csr(VX_CSR_FFLAGS, this->get_csr(VX_CSR_FFLAGS, t, wid) | fflags, t, wid);
}
this->update_fcrs(fflags, t, wid);
}
rd_write = true;
break;
Expand Down
2 changes: 2 additions & 0 deletions sim/simx/main.cpp
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Expand Up @@ -120,7 +120,9 @@ int main(int argc, char **argv) {
#endif
// run simulation
// vector test exitcode is a special case
#ifdef EXT_V_ENABLE
if (vector_test) return processor.run();
#endif
// else continue as normal
processor.run();

Expand Down
2 changes: 2 additions & 0 deletions sim/simx/processor.cpp
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Expand Up @@ -127,7 +127,9 @@ int ProcessorImpl::run() {
done = false;
continue;
}
#ifdef EXT_V_ENABLE
exitcode |= cluster->get_exitcode();
#endif
}
perf_mem_latency_ += perf_mem_pending_reads_;
} while (!done);
Expand Down
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