add power placer for pure art designs

Makefile

@@ -31,6 +31,10 @@ MAG_MACROS_SRC := $(foreach macro,$(TARGET_MACRO),$(filter %$(macro).mag,$(MAG_S
 GDS_MACROS_SRC := $(foreach macro,$(TARGET_MACRO),$(filter %$(macro).gds,$(GDS_SOURCES)))
 LEF_MACROS_SRC := $(foreach macro,$(TARGET_MACRO),$(filter %$(macro).lef,$(LEF_SOURCES)))
 
+# Name of top module
+TOP_NAME ?= tt_um_macro_test_wrapper
+PURE_ART ?= 1
+
 ifeq ($(words $(MAKECMDGOALS)),2)
   # check if we have a mag or GDS for the macro
   ifeq ($(or $(MAG_MACROS_SRC),$(GDS_MACROS_SRC)),)
@@ -91,6 +95,10 @@ tt_harden_top: preproc
 	mkdir -p runs/$(TAGET_MACRO)
 	ln -sf $(TARGET_MACRO)_config.json src/config.json
 	./tt/tt_tool.py --harden --openlane2
+	cp runs/wokwi/final/gds/* gds/final/
+	cp runs/wokwi/final/mag/* mag/final/
+	cp runs/wokwi/final/lef/* lef/final/
+	PURE_ART=$(PURE_ART) TOP_NAME=$(TOP_NAME) MACRO_NAME=$(TARGET_MACRO) magic -noconsole -dnull ./tcl/place_power_pins.tcl
 
 tt_render_final:
 	mkdir -p render

README.md

@@ -12,7 +12,7 @@ _Note: Work In Progress_
 - GDSPY: `apt install python3-gdspy`
   - required to add boundary layers to GDS files and to remove output driver cells: 
 - `rsvg-convert`: For SVG based input images
-
+- `magic` if your design is a pure art design, to manually add the VPWR, VGND nets and remove the output drivers.
 
 ## Getting Started
 
@@ -26,23 +26,10 @@ _Note: Work In Progress_
 4. Make a copy of `src/ttlogo_config.json` as `src/<my_macro_name>_config.json`
    - Edit the `VERILOG_DEFINES` and `MACROS` inside the config options to specify which macro you would like to place.
    - If you are using this to add a logo to an existing project, you need to delete the flow in the config, and use the normal classic flow.
-
-5. Run `make tt_harden_top <my_macro_name>`
-
-DO NOT run this step if your design has existing digital logic, this is for pure art macro designs!
-
-6. The output of your design should now be in `runs/wokwi/final`, now one last thing needs to be done
-before submitting via adding your top-level macro to the `gds/final` folder. The output drivers need to
-be removed from the final GDS. This can be done using the following command:
-    - `./script/gds_rm_outputs.py runs/wokwi/final/gds/tt_um_macro_test_wrapper.gds`
-    - _Note:_ Replace `tt_um_macro_test_wrapper` with the name of your top-level module.
-
-7. Now the final design files can be copied to `gds/final` and `lef/final`:
-
-```bash
-cp runs/wokwi/final/gds/tt_um_macro_test_wrapper.gds gds/final
-cp runs/wokwi/final/lef/tt_um_macro_test_wrapper.lef lef/final
-```
+5. Run `make tt_harden_top <my_macro_name>`.
+   - If your design in purely art, and has no logic, please do: `PURE_ART=1 make tt_harden_top <my_macro_name>`
+   - If you need to override the top module name set `TOP_NAME=` as well.
+6. The final designs are now made available in {gds,mag,lef}/final.
 
 ---
 

lef/final/tt_um_macro_test_wrapper.lef

@@ -2,9 +2,9 @@ VERSION 5.7 ;
   NOWIREEXTENSIONATPIN ON ;
   DIVIDERCHAR "/" ;
   BUSBITCHARS "[]" ;
-MACRO tt_um_macro_test_wrapper
+MACRO mag/final/tt_um_macro_test_wrapper
   CLASS BLOCK ;
-  FOREIGN tt_um_macro_test_wrapper ;
+  FOREIGN mag/final/tt_um_macro_test_wrapper ;
   ORIGIN 0.000 0.000 ;
   SIZE 334.880 BY 225.760 ;
   PIN clk
@@ -351,22 +351,26 @@ MACRO tt_um_macro_test_wrapper
         RECT 74.830 224.760 75.130 225.760 ;
     END
   END uo_out[7]
+  PIN VPWR
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met4 ;
+        RECT 1.000 5.000 3.000 220.760 ;
+    END
+  END VPWR
+  PIN VGND
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER met4 ;
+        RECT 4.000 5.000 6.000 220.760 ;
+    END
+  END VGND
   OBS
-      LAYER nwell ;
-        RECT -0.190 1.305 2.030 2.910 ;
-        RECT 0.000 0.105 2.030 1.305 ;
-        RECT 0.000 0.000 0.145 0.105 ;
-      LAYER pwell ;
-        RECT 0.145 -0.085 0.315 0.105 ;
-      LAYER nwell ;
-        RECT 0.315 0.000 2.030 0.105 ;
-      LAYER li1 ;
-        RECT 0.000 -0.085 1.840 2.805 ;
-      LAYER met1 ;
-        RECT 0.000 -0.240 1.840 2.960 ;
       LAYER met2 ;
         RECT 50.000 50.000 59.800 55.600 ;
   END
-END tt_um_macro_test_wrapper
+END mag/final/tt_um_macro_test_wrapper
 END LIBRARY
 

mag/final/tt_um_macro_test_wrapper.mag

@@ -0,0 +1,153 @@
+magic
+tech sky130A
+timestamp 1725862423
+<< checkpaint >>
+rect -530 926 1230 22706
+rect 4370 4370 6610 6190
+rect -649 -130 1230 926
+rect -649 -654 833 -130
+<< metal4 >>
+rect 3067 22476 3097 22576
+rect 3343 22476 3373 22576
+rect 3619 22476 3649 22576
+rect 3895 22476 3925 22576
+rect 4171 22476 4201 22576
+rect 4447 22476 4477 22576
+rect 4723 22476 4753 22576
+rect 4999 22476 5029 22576
+rect 5275 22476 5305 22576
+rect 5551 22476 5581 22576
+rect 5827 22476 5857 22576
+rect 6103 22476 6133 22576
+rect 6379 22476 6409 22576
+rect 6655 22476 6685 22576
+rect 6931 22476 6961 22576
+rect 7207 22476 7237 22576
+rect 7483 22476 7513 22576
+rect 7759 22476 7789 22576
+rect 8035 22476 8065 22576
+rect 8311 22476 8341 22576
+rect 8587 22476 8617 22576
+rect 8863 22476 8893 22576
+rect 9139 22476 9169 22576
+rect 9415 22476 9445 22576
+rect 9691 22476 9721 22576
+rect 9967 22476 9997 22576
+rect 10243 22476 10273 22576
+rect 10519 22476 10549 22576
+rect 10795 22476 10825 22576
+rect 11071 22476 11101 22576
+rect 11347 22476 11377 22576
+rect 11623 22476 11653 22576
+rect 11899 22476 11929 22576
+rect 12175 22476 12205 22576
+rect 12451 22476 12481 22576
+rect 12727 22476 12757 22576
+rect 13003 22476 13033 22576
+rect 13279 22476 13309 22576
+rect 13555 22476 13585 22576
+rect 13831 22476 13861 22576
+rect 14107 22476 14137 22576
+rect 14383 22476 14413 22576
+rect 14659 22476 14689 22576
+rect 100 500 300 22076
+rect 400 500 600 22076
+use ttlogo  um_ttlogo
+timestamp 1554431724
+transform 1 0 5000 0 1 5000
+box 0 0 980 560
+<< labels >>
+flabel metal4 s 14383 22476 14413 22576 0 FreeSans 240 90 0 0 clk
+port 0 nsew signal input
+flabel metal4 s 14659 22476 14689 22576 0 FreeSans 240 90 0 0 ena
+port 1 nsew signal input
+flabel metal4 s 14107 22476 14137 22576 0 FreeSans 240 90 0 0 rst_n
+port 2 nsew signal input
+flabel metal4 s 13831 22476 13861 22576 0 FreeSans 240 90 0 0 ui_in[0]
+port 3 nsew signal input
+flabel metal4 s 13555 22476 13585 22576 0 FreeSans 240 90 0 0 ui_in[1]
+port 4 nsew signal input
+flabel metal4 s 13279 22476 13309 22576 0 FreeSans 240 90 0 0 ui_in[2]
+port 5 nsew signal input
+flabel metal4 s 13003 22476 13033 22576 0 FreeSans 240 90 0 0 ui_in[3]
+port 6 nsew signal input
+flabel metal4 s 12727 22476 12757 22576 0 FreeSans 240 90 0 0 ui_in[4]
+port 7 nsew signal input
+flabel metal4 s 12451 22476 12481 22576 0 FreeSans 240 90 0 0 ui_in[5]
+port 8 nsew signal input
+flabel metal4 s 12175 22476 12205 22576 0 FreeSans 240 90 0 0 ui_in[6]
+port 9 nsew signal input
+flabel metal4 s 11899 22476 11929 22576 0 FreeSans 240 90 0 0 ui_in[7]
+port 10 nsew signal input
+flabel metal4 s 11623 22476 11653 22576 0 FreeSans 240 90 0 0 uio_in[0]
+port 11 nsew signal input
+flabel metal4 s 11347 22476 11377 22576 0 FreeSans 240 90 0 0 uio_in[1]
+port 12 nsew signal input
+flabel metal4 s 11071 22476 11101 22576 0 FreeSans 240 90 0 0 uio_in[2]
+port 13 nsew signal input
+flabel metal4 s 10795 22476 10825 22576 0 FreeSans 240 90 0 0 uio_in[3]
+port 14 nsew signal input
+flabel metal4 s 10519 22476 10549 22576 0 FreeSans 240 90 0 0 uio_in[4]
+port 15 nsew signal input
+flabel metal4 s 10243 22476 10273 22576 0 FreeSans 240 90 0 0 uio_in[5]
+port 16 nsew signal input
+flabel metal4 s 9967 22476 9997 22576 0 FreeSans 240 90 0 0 uio_in[6]
+port 17 nsew signal input
+flabel metal4 s 9691 22476 9721 22576 0 FreeSans 240 90 0 0 uio_in[7]
+port 18 nsew signal input
+flabel metal4 s 4999 22476 5029 22576 0 FreeSans 240 90 0 0 uio_oe[0]
+port 19 nsew signal output
+flabel metal4 s 4723 22476 4753 22576 0 FreeSans 240 90 0 0 uio_oe[1]
+port 20 nsew signal output
+flabel metal4 s 4447 22476 4477 22576 0 FreeSans 240 90 0 0 uio_oe[2]
+port 21 nsew signal output
+flabel metal4 s 4171 22476 4201 22576 0 FreeSans 240 90 0 0 uio_oe[3]
+port 22 nsew signal output
+flabel metal4 s 3895 22476 3925 22576 0 FreeSans 240 90 0 0 uio_oe[4]
+port 23 nsew signal output
+flabel metal4 s 3619 22476 3649 22576 0 FreeSans 240 90 0 0 uio_oe[5]
+port 24 nsew signal output
+flabel metal4 s 3343 22476 3373 22576 0 FreeSans 240 90 0 0 uio_oe[6]
+port 25 nsew signal output
+flabel metal4 s 3067 22476 3097 22576 0 FreeSans 240 90 0 0 uio_oe[7]
+port 26 nsew signal output
+flabel metal4 s 7207 22476 7237 22576 0 FreeSans 240 90 0 0 uio_out[0]
+port 27 nsew signal output
+flabel metal4 s 6931 22476 6961 22576 0 FreeSans 240 90 0 0 uio_out[1]
+port 28 nsew signal output
+flabel metal4 s 6655 22476 6685 22576 0 FreeSans 240 90 0 0 uio_out[2]
+port 29 nsew signal output
+flabel metal4 s 6379 22476 6409 22576 0 FreeSans 240 90 0 0 uio_out[3]
+port 30 nsew signal output
+flabel metal4 s 6103 22476 6133 22576 0 FreeSans 240 90 0 0 uio_out[4]
+port 31 nsew signal output
+flabel metal4 s 5827 22476 5857 22576 0 FreeSans 240 90 0 0 uio_out[5]
+port 32 nsew signal output
+flabel metal4 s 5551 22476 5581 22576 0 FreeSans 240 90 0 0 uio_out[6]
+port 33 nsew signal output
+flabel metal4 s 5275 22476 5305 22576 0 FreeSans 240 90 0 0 uio_out[7]
+port 34 nsew signal output
+flabel metal4 s 9415 22476 9445 22576 0 FreeSans 240 90 0 0 uo_out[0]
+port 35 nsew signal output
+flabel metal4 s 9139 22476 9169 22576 0 FreeSans 240 90 0 0 uo_out[1]
+port 36 nsew signal output
+flabel metal4 s 8863 22476 8893 22576 0 FreeSans 240 90 0 0 uo_out[2]
+port 37 nsew signal output
+flabel metal4 s 8587 22476 8617 22576 0 FreeSans 240 90 0 0 uo_out[3]
+port 38 nsew signal output
+flabel metal4 s 8311 22476 8341 22576 0 FreeSans 240 90 0 0 uo_out[4]
+port 39 nsew signal output
+flabel metal4 s 8035 22476 8065 22576 0 FreeSans 240 90 0 0 uo_out[5]
+port 40 nsew signal output
+flabel metal4 s 7759 22476 7789 22576 0 FreeSans 240 90 0 0 uo_out[6]
+port 41 nsew signal output
+flabel metal4 s 7483 22476 7513 22576 0 FreeSans 240 90 0 0 uo_out[7]
+port 42 nsew signal output
+flabel metal4 100 500 300 22076 1 FreeSans 200 0 0 0 VPWR
+port 43 nsew power bidirectional
+flabel metal4 400 500 600 22076 1 FreeSans 200 0 0 0 VGND
+port 44 nsew ground bidirectional
+<< properties >>
+string FIXED_BBOX 0 0 33488 22576
+string LEFclass BLOCK
+<< end >>

script/gds_add_pnb.py

@@ -1,4 +1,6 @@
 #!/usr/bin/env python3
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileCopyrightText: 2024 Dayton Pidhirney
 import sys, os
 import gdspy