Added Verilator Simulation Control HDL code and updates to software a…

…nd make files
wyvernSemi · Dec 5, 2024 · 91bf976 · 91bf976
1 parent 37b0b65
commit 91bf976
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Showing 11 changed files with 198 additions and 13 deletions.
diff --git a/code/VProcClass.h b/code/VProcClass.h
@@ -23,6 +23,9 @@
 // C++ API class wrapper for VProc C API
 //=====================================================================
 
+#ifndef _VPROCCLASS_H_
+#define _VPROCCLASS_H_
+
 extern "C"
 {
 #include "VUser.h"
@@ -102,4 +105,6 @@ class VProc
         int      diffoff = loff - foff;
         return bytelen/4 + ((diffoff < 0) ? 1 : 0) + ((bytelen%4) ? 1 : 0);
     };
-};
+};
+
+#endif
diff --git a/code/VProcIrqClass.h b/code/VProcIrqClass.h
@@ -25,6 +25,9 @@
 
 #include "VProcClass.h"
 
+#ifndef _VPROCCLASS_IRQ_H_
+#define _VPROCCLASS_IRQ_H_
+
 class VProcIrqClass : public VProc
 {
 public:
@@ -204,3 +207,5 @@ class VProcIrqClass : public VProc
     uint32_t   edgeTriggered;      // Mark irq vector edge triggerd inputs
     pIntFunc_t isr[MAXINTERRUPTS]; // pointers to ISR functions
 };
+
+#endif
diff --git a/test/makefile.common b/test/makefile.common
@@ -26,8 +26,10 @@
 #    SRCDIR             : Location of VProc source files
 #    USRCDIR            : Location of user C/C++ source files
 #    MEMMODELDIR        : Location of optional memory model source files (set to . if unused)
+#    AUXDIR             : Location of optional auxilary user source files (set to . if unused)
 #    USER_C             : List of user C/C++ source files (no path)
 #    MEM_C              : Optional list of memory model C/C++ source files (no path)
+#    AUX_C              : Optional list of auxilary user C/C++ source files (no path)
 #    VOBJDIR            : Location of temporary directory for object files
 #    OSTYPE             : OS type. "Linux" for Linux else defaults to MSYS2/mingw64 on windows
 #    SIMINCLUDEFLAG     : Include flag (-I) for logic simulator's include path
@@ -52,14 +54,18 @@ USER_CPP_BASE       = $(notdir $(filter %cpp, $(USER_C)))
 USER_C_BASE         = $(notdir $(filter %c,   $(USER_C)))
 MEM_CPP_BASE        = $(notdir $(filter %cpp, $(MEM_C)))
 MEM_C_BASE          = $(notdir $(filter %c,   $(MEM_C)))
+AUX_CPP_BASE        = $(notdir $(filter %cpp, $(AUX_C)))
+AUX_C_BASE          = $(notdir $(filter %c,   $(AUX_C)))
 
 # Create list of object files (excluding any veriuser object)
 VOBJS               = $(addprefix $(VOBJDIR)/,            \
                           $(USER_C_BASE:%.c=%.o)          \
                           $(USER_CPP_BASE:%.cpp=%.o)      \
                           $(VPROC_C:%.c=%.o)              \
                           $(MEM_C_BASE:%.c=%.o)           \
-                          $(MEM_CPP_BASE:%.cpp=%.o))
+                          $(MEM_CPP_BASE:%.cpp=%.o)       \
+                          $(AUX_C_BASE:%.c=%.o)           \
+                          $(AUX_CPP_BASE:%.cpp=%.o))
 
 # Set OS specific variables between Linux and Windows (MinGW)
 ifeq ($(OSTYPE), Linux)
@@ -119,6 +125,14 @@ $(VOBJDIR)/%.o: $(MEMMODELDIR)/%.c $(MEMMODELDIR)/*.h
 $(VOBJDIR)/%.o: $(MEMMODELDIR)/%.cpp $(MEMMODELDIR)/*.h
 	@$(C++) -c -fPIC $(CFLAGS) $< -o $@
 
+# Rule to build (any) auxilary C sources
+$(VOBJDIR)/%.o: $(AUXDIR)/%.c $(AUXDIR)/*.h
+	@$(CC) -c -fPIC $(CFLAGS) $< -o $@
+
+# Rule to build (any) memory model C++ sources
+$(VOBJDIR)/%.o: $(AUXDIR)/%.cpp $(AUXDIR)/*.h
+	@$(C++) -c -fPIC $(CFLAGS) $< -o $@
+
 # Rule to build VProc library
 $(VLIB) : $(VOBJS) $(VOBJDIR)
 	@ar cr $(VLIB) $(VOBJS)

diff --git a/test/makefile.verilator b/test/makefile.verilator
@@ -57,6 +57,10 @@ endif
 MEM_C              =
 MEMMODELDIR        = .
 
+# Optional auxilary user code definitions
+AUX_C              =
+AUXDIR             = .
+
 #......................................................
 # Common logic simulator flags
 #.....................................................

diff --git a/verilator/src/VerilatorSimCtrl.cpp b/verilator/src/VerilatorSimCtrl.cpp
@@ -283,7 +283,7 @@ static int parse_command(const std::string &command, VProc *vp, uint32_t &cyc_co
 
 void rungtkwave (void)
 {
-    system("gtkwave -A waves.fst > gtkwave.log 2>&1");
+    system("gtkwave -A waves.vcd > gtkwave.log 2>&1");
 }
 
 // ---------------------------------------------

diff --git a/verilator/src/VerilatorSimCtrl.h b/verilator/src/VerilatorSimCtrl.h
@@ -32,6 +32,8 @@
 #include <cmath>
 #include <regex>
 
+#include "VProcClass.h"
+
 #ifndef _VERILATORSIMCTRL_H_
 #define _VERILATORSIMCTRL_H_
 

diff --git a/verilator/src/versim.cpp b/verilator/src/versim.cpp
@@ -20,12 +20,14 @@
 //
 // ====================================================================
 
-#include <verilated_fst_c.h>
+//#include <verilated_fst_c.h>
+#include <verilated_vcd_c.h>
 
 #include "verilated.h"
 #include "Vtest.h"
 
-static VerilatedFstC *trace_p  = new VerilatedFstC;
+//static VerilatedFstC *trace_p  = new VerilatedFstC;
+static VerilatedVcdC *trace_p  = new VerilatedVcdC;
 static bool           do_flush = true;
 
 //-----------------------------------------
@@ -62,7 +64,8 @@ int main(int argc, char** argv)
    test_p->trace(trace_p, 20);
 
    // Open a wave form file
-   trace_p->open("waves.fst");
+   //trace_p->open("waves.fst");
+   trace_p->open("waves.vcd");
 
    // Simulate until $finish or no events left to process
    while (!contextp->gotFinish())

diff --git a/verilator/test/makefile b/verilator/test/makefile
@@ -52,7 +52,8 @@ SIMDEFS            = -GDISABLE_SIM_CTRL=0
 WORKDIR            = work
 
 # set to -GVCD_DUMP=1 to generate VCD ouput, or blank for none
-VCDFLAG            = --trace-fst -GDISABLE_SIM_CTRL=1
+#VCDFLAG            = --trace-fst -GDISABLE_SIM_CTRL=1
+VCDFLAG            = --trace -GDISABLE_SIM_CTRL=1
 
 # Set to --timing for delta cycle support, or blank for no delta-cycle
 TIMINGFLAG         = --timing
@@ -66,10 +67,10 @@ SIMCFLAGS          = $(CPPSTD) -DVL_TIME_CONTEXT -Wno-attributes
 OSTYPE             := $(shell uname)
 
 ifeq ($(OSTYPE), Linux)
-  SIMFLAGSSO       = -Wl,-E -lrt -rdynamic
+  SIMFLAGSLD       = -Wl,-E -lrt -rdynamic
   SIMEXE           = $(WORKDIR)/V$(SIM_TOP)
 else
-  SIMFLAGSSO       = -Wl,-export-all-symbols
+  SIMFLAGSLD       = -Wl,-export-all-symbols
   SIMEXE             = $(WORKDIR)/V$(SIM_TOP).exe
 endif
 
@@ -86,13 +87,14 @@ SIMFLAGS           = --cc -sv -exe $(VERIMAIN)              \
                      --top $(SIM_TOP)                       \
                      -MAKEFLAGS "--quiet"                   \
                      -CFLAGS "$(SIMCFLAGS)"                 \
-                     -LDFLAGS "$(SIMFLAGSSO)                \
+                     -LDFLAGS "$(SIMFLAGSLD)                \
                      $(VSCCODE)                             \
                      -Wl,-whole-archive -L../ -lvproc -Wl,-no-whole-archive -ldl"
 
 
 
-WAVEFILE           = waves.fst
+#WAVEFILE           = waves.fst
+WAVEFILE           = waves.vcd
 WAVESAVEFILE       = wave.gtkw
 
 SPACE              =

diff --git a/verilator/test/usercode/VUserMain0.h b/verilator/test/usercode/VUserMain0.h
@@ -23,8 +23,6 @@
 #ifndef _VUSERMAIN0_CPP_
 #define _VUSERMAIN0_CPP_
 
-
-#include "VProcClass.h"
 #include "VerilatorSimCtrl.h"
 
 #define SLEEPFOREVER {while(1) VTick(0x7fffffff, node);}

diff --git a/verilator/verilator_sim_ctrl.sv b/verilator/verilator_sim_ctrl.sv
@@ -0,0 +1,126 @@
+// ====================================================================
+//
+// SystemVerilog VProc Verilator simulation control module
+//
+// Copyright (c) 2024 Simon Southwell.
+//
+// This file is part of VProc.
+//
+// VProc is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// VProc is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with VProc. If not, see <http://www.gnu.org/licenses/>.
+//
+// ====================================================================
+
+`include "verilator_sim_ctrl.vh"
+
+module verilator_sim_ctrl
+#(parameter                  NODE             = 0,
+                             CLK_PERIOD_PS    = 10000,
+                             DISABLE_SIM_CTRL = 0
+
+)
+(
+    input                    clk,
+    output reg [31:0]        cycle_count
+);
+
+wire [31:0]                  addr;
+wire [31:0]                  dataout;
+reg  [31:0]                  datain;
+wire                         we;
+wire                         rd;
+
+wire                         update;
+
+// -----------------------------------------
+// Initial
+// -----------------------------------------
+
+initial
+begin
+  cycle_count                = 0;
+end
+
+generate
+
+if (DISABLE_SIM_CTRL == 0) begin
+
+
+// -----------------------------------------
+// Read process
+// -----------------------------------------
+
+  always @(negedge clk)
+  begin
+
+    case (addr)
+      `VSC_CYC_COUNT_ADDR:
+        datain                 <= cycle_count;
+      `VSC_CLK_PERIOD_ADDR:
+        datain                 <= CLK_PERIOD_PS;
+      default:
+        datain                 <= 32'h0;
+    endcase
+  end
+
+// -----------------------------------------
+// write process
+// -----------------------------------------
+
+  always @(posedge clk)
+  begin
+    cycle_count                <= cycle_count + 1;
+
+    if (we)
+    begin
+      case (addr)
+        `VSC_FINISH_ADDR: if (dataout[0]) $finish;
+        default;
+      endcase
+    end
+  end
+
+// -----------------------------------------
+//  VProc instantiation
+// -----------------------------------------
+
+  VProc
+    #(
+      .DISABLE_DELTA          (1)
+    ) vp
+    (
+      .Clk                    (clk),
+
+      // Bus
+      .Addr                   (addr),
+      .DataOut                (dataout),
+      .WE                     (we),
+      .WRAck                  (we),
+      .DataIn                 (datain),
+      .RD                     (rd),
+      .RDAck                  (rd),
+
+      // Interrupts
+      .Interrupt              (0),
+
+      // Delta cycle control
+      .Update                 (update),
+      .UpdateResponse         (update),
+
+      .Node                   (NODE[3:0])
+  );
+
+end
+endgenerate
+
+endmodule
diff --git a/verilator/verilator_sim_ctrl.vh b/verilator/verilator_sim_ctrl.vh
@@ -0,0 +1,26 @@
+// ====================================================================
+//
+// SystemVerilog VProc Verilator simulation control module header
+//
+// Copyright (c) 2024 Simon Southwell.
+//
+// This file is part of VProc.
+//
+// VProc is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// VProc is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with VProc. If not, see <http://www.gnu.org/licenses/>.
+//
+// ====================================================================
+
+`define VSC_CYC_COUNT_ADDR   32'h0
+`define VSC_CLK_PERIOD_ADDR  32'h1
+`define VSC_FINISH_ADDR      32'h2