Skip to content

Commit

Permalink
updated for ghidra 9.2.2
Browse files Browse the repository at this point in the history
updated for ghidra 9.2.2
  • Loading branch information
zeroKilo committed Jan 30, 2021
1 parent 94af346 commit e114c84
Show file tree
Hide file tree
Showing 16 changed files with 772 additions and 187 deletions.
412 changes: 246 additions & 166 deletions .classpath

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion .project
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
<link>
<name>Ghidra</name>
<type>2</type>
<location>C:/Users/wv/Desktop/ghidra_9.1.2_PUBLIC</location>
<location>C:/Users/wv/Desktop/ghidra</location>
</link>
</linkedResources>
</projectDescription>
15 changes: 15 additions & 0 deletions data/README.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
The "data" directory is intended to hold data files that will be used by this module and will
not end up in the .jar file, but will be present in the zip or tar file. Typically, data
files are placed here rather than in the resources directory if the user may need to edit them.

An optional data/languages directory can exist for the purpose of containing various Sleigh language
specification files and importer opinion files.

The data/build.xml is used for building the contents of the data/languages directory.

The skel language definition has been commented-out within the skel.ldefs file so that the
skeleton language does not show-up within Ghidra.

See the Sleigh language documentation (docs/languages/sleigh.htm or sleigh.pdf) for details
on Sleigh language specification syntax.

50 changes: 50 additions & 0 deletions data/build.xml
Original file line number Diff line number Diff line change
@@ -0,0 +1,50 @@
<?xml version="1.0" encoding="UTF-8"?>

<!--
+ Compile sleigh languages within this module.
+ Sleigh compiler options are read from the sleighArgs.txt file.
+ Eclipse: right-click on this file and choose menu item "Run As->Ant Build"
-->

<project name="privateBuildDeveloper" default="sleighCompile">

<property name="sleigh.compile.class" value="ghidra.pcodeCPort.slgh_compile.SleighCompile"/>

<!--Import optional ant properties. GhidraDev Eclipse plugin produces this so this file can find the Ghidra installation-->
<import file="../.antProperties.xml" optional="false" />

<target name="sleighCompile">

<!-- If language module is detached from installation, get Ghidra installation directory path from imported properties -->
<property name="framework.path" value="${ghidra.install.dir}/Ghidra/Framework"/>

<path id="sleigh.class.path">
<fileset dir="${framework.path}/SoftwareModeling/lib">
<include name="*.jar"/>
</fileset>
<fileset dir="${framework.path}/Generic/lib">
<include name="*.jar"/>
</fileset>
<fileset dir="${framework.path}/Utility/lib">
<include name="*.jar"/>
</fileset>
</path>

<available classname="${sleigh.compile.class}" classpathref="sleigh.class.path" property="sleigh.compile.exists"/>

<fail unless="sleigh.compile.exists" />

<java classname="${sleigh.compile.class}"
classpathref="sleigh.class.path"
fork="true"
failonerror="true">
<jvmarg value="-Xmx2048M"/>
<arg value="-i"/>
<arg value="sleighArgs.txt"/>
<arg value="-a"/>
<arg value="./languages"/>
</java>

</target>

</project>
129 changes: 129 additions & 0 deletions data/languages/skel.cspec
Original file line number Diff line number Diff line change
@@ -0,0 +1,129 @@
<?xml version="1.0" encoding="UTF-8"?>

<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/compiler_spec.rxg -->

<compiler_spec>
<data_organization>
<pointer_size value="2" />
</data_organization>
<global>
<range space="ram"/>
<range space="io"/>
</global>
<stackpointer register="SP" space="ram"/>
<segmentop space="ram" userop="segment" baseinsize="2" innerinsize="2" farpointer="yes">
<baseop code="INT_ZEXT"/>
<baseop code="INT_LEFT" value="12"/>
<innerop code="INT_ZEXT"/>
<constresolve>
<register name="rBBR"/>
</constresolve>
</segmentop>
<default_proto>
<prototype name="__asmA" extrapop="2" stackshift="2" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="BC"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="HL"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="DE"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IY"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="BC_"/>
<register name="HL_"/>
<register name="DE_"/>
<register name="AF_"/>
<register name="rBBR"/>
</unaffected>
</prototype>
</default_proto>
<prototype name="__asmAF" extrapop="2" stackshift="2" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="BC"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="HL"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="DE"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IY"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="AF"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="rBBR"/>
<register name="BC_"/>
<register name="HL_"/>
<register name="DE_"/>
<register name="AF_"/>
</unaffected>
</prototype>
<prototype name="__stdcall" extrapop="2" stackshift="2">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="BC"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="HL"/>
</pentry>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="AF"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="rBBR"/>
<register name="BC_"/>
<register name="HL_"/>
<register name="DE_"/>
<register name="AF_"/>
</unaffected>
</prototype>
</compiler_spec>
20 changes: 20 additions & 0 deletions data/languages/skel.ldefs
Original file line number Diff line number Diff line change
@@ -0,0 +1,20 @@
<?xml version="1.0" encoding="UTF-8"?>

<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/language_definitions.rxg -->

<language_definitions>
<!-- Uncomment the following to make the language available in Ghidra -->
<!--
<language processor="Skel"
endian="little"
size="16"
variant="default"
version="1.0"
slafile="skel.sla"
processorspec="skel.pspec"
id="skel:LE:16:default">
<description>Skeleton Language Module</description>
<compiler name="default" spec="skel.cspec" id="default"/>
</language>
-->
</language_definitions>
12 changes: 12 additions & 0 deletions data/languages/skel.opinion
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
<opinions>
<!-- Example of importer opinions - commented-out to prevent use by Ghidra -->
<!-- The primary and secondary constraint values must be specifide as a decimal string -->
<!--
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<constraint primary="40" secondary="123" processor="Skel" size="16" variant="default" />
</constraint>
<constraint loader="MS Common Object File Format (COFF)" compilerSpecID="default">
<constraint primary="61" processor="Skel" size="16" variant="default" />
</constraint>
-->
</opinions>
23 changes: 23 additions & 0 deletions data/languages/skel.pspec
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
<?xml version="1.0" encoding="UTF-8"?>

<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/processor_spec.rxg -->

<processor_spec>
<programcounter register="PC"/>
<register_data>
<register name="AF_" group="Alt"/>
<register name="BC_" group="Alt"/>
<register name="DE_" group="Alt"/>
<register name="HL_" group="Alt"/>
</register_data>
<default_symbols>
<symbol name="RST0" address="ram:0000" entry="true"/>
<symbol name="RST1" address="ram:0008" entry="false"/>
<symbol name="RST2" address="ram:0010" entry="false"/>
<symbol name="RST3" address="ram:0018" entry="false"/>
<symbol name="RST4" address="ram:0020" entry="false"/>
<symbol name="RST5" address="ram:0028" entry="false"/>
<symbol name="RST6" address="ram:0030" entry="false"/>
<symbol name="RST7" address="ram:0038" entry="false"/>
</default_symbols>
</processor_spec>
Loading

0 comments on commit e114c84

Please sign in to comment.