Add riscv implemention

zifeihan · Mar 25, 2024 · 513963a · 513963a
1 parent 4aed4b5
commit 513963a
Showing 1 changed file with 38 additions and 4 deletions.
diff --git a/src/hotspot/cpu/riscv/riscv_v.ad b/src/hotspot/cpu/riscv/riscv_v.ad
@@ -1313,11 +1313,12 @@ instruct reduce_addL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
   ins_pipe(pipe_slow);
 %}
 
-instruct reduce_addF(fRegF dst, fRegF src1, vReg src2, vReg tmp) %{
+instruct reduce_addF_ordered(fRegF dst, fRegF src1, vReg src2, vReg tmp) %{
+  predicate(!n->as_Reduction()->is_associative());
   match(Set dst (AddReductionVF src1 src2));
   effect(TEMP tmp);
   ins_cost(VEC_COST);
-  format %{ "reduce_addF $dst, $src1, $src2\t# KILL $tmp" %}
+  format %{ "reduce_addF_ordered $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
     __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this, $src2));
     __ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1$$FloatRegister);
@@ -1328,11 +1329,28 @@ instruct reduce_addF(fRegF dst, fRegF src1, vReg src2, vReg tmp) %{
   ins_pipe(pipe_slow);
 %}
 
-instruct reduce_addD(fRegD dst, fRegD src1, vReg src2, vReg tmp) %{
+instruct reduce_addF_unordered(fRegF dst, fRegF src1, vReg src2, vReg tmp) %{
+  predicate(n->as_Reduction()->is_associative());
+  match(Set dst (AddReductionVF src1 src2));
+  effect(TEMP tmp);
+  ins_cost(VEC_COST);
+  format %{ "reduce_addF_unordered $dst, $src1, $src2\t# KILL $tmp" %}
+  ins_encode %{
+    __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this, $src2));
+    __ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1$$FloatRegister);
+    __ vfredusum_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg),
+                    as_VectorRegister($tmp$$reg));
+    __ vfmv_f_s($dst$$FloatRegister, as_VectorRegister($tmp$$reg));
+  %}
+  ins_pipe(pipe_slow);
+%}
+
+instruct reduce_addD_ordered(fRegD dst, fRegD src1, vReg src2, vReg tmp) %{
+  predicate(!n->as_Reduction()->is_associative());
   match(Set dst (AddReductionVD src1 src2));
   effect(TEMP tmp);
   ins_cost(VEC_COST);
-  format %{ "reduce_addD $dst, $src1, $src2\t# KILL $tmp" %}
+  format %{ "reduce_addD_ordered $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
     __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this, $src2));
     __ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1$$FloatRegister);
@@ -1343,6 +1361,22 @@ instruct reduce_addD(fRegD dst, fRegD src1, vReg src2, vReg tmp) %{
   ins_pipe(pipe_slow);
 %}
 
+instruct reduce_addD_unordered(fRegD dst, fRegD src1, vReg src2, vReg tmp) %{
+  predicate(n->as_Reduction()->is_associative());
+  match(Set dst (AddReductionVD src1 src2));
+  effect(TEMP tmp);
+  ins_cost(VEC_COST);
+  format %{ "reduce_addD_unordered $dst, $src1, $src2\t# KILL $tmp" %}
+  ins_encode %{
+    __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this, $src2));
+    __ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1$$FloatRegister);
+    __ vfredusum_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg),
+                    as_VectorRegister($tmp$$reg));
+    __ vfmv_f_s($dst$$FloatRegister, as_VectorRegister($tmp$$reg));
+  %}
+  ins_pipe(pipe_slow);
+%}
+
 // vector add reduction - predicated
 
 instruct reduce_addI_masked(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegMask_V0 v0, vReg tmp) %{