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zifeihan committed May 28, 2024
1 parent 5f26d42 commit ac335ba
Showing 1 changed file with 84 additions and 84 deletions.
168 changes: 84 additions & 84 deletions src/hotspot/cpu/riscv/riscv_v.ad
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Original file line number Diff line number Diff line change
Expand Up @@ -389,60 +389,60 @@ instruct vadd_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{

// vector-immediate add (unpredicated)

instruct vadd_immI(vReg dst_src, immI5 con) %{
match(Set dst_src (AddVB dst_src (Replicate con)));
match(Set dst_src (AddVS dst_src (Replicate con)));
match(Set dst_src (AddVI dst_src (Replicate con)));
format %{ "vadd_immI $dst_src, $dst_src, $con" %}
instruct vadd_immI(vReg dst, vReg src1, immI5 con) %{
match(Set dst (AddVB src1 (Replicate con)));
match(Set dst (AddVS src1 (Replicate con)));
match(Set dst (AddVI src1 (Replicate con)));
format %{ "vadd_immI $dst, $src1, $con" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ vsetvli_helper(bt, Matcher::vector_length(this));
__ vadd_vi(as_VectorRegister($dst_src$$reg),
as_VectorRegister($dst_src$$reg),
__ vadd_vi(as_VectorRegister($dst$$reg),
as_VectorRegister($src1$$reg),
$con$$constant);
%}
ins_pipe(pipe_slow);
%}

instruct vadd_immL(vReg dst_src, immL5 con) %{
match(Set dst_src (AddVL dst_src (Replicate con)));
format %{ "vadd_immL $dst_src, $dst_src, $con" %}
instruct vadd_immL(vReg dst, vReg src1, immL5 con) %{
match(Set dst (AddVL src1 (Replicate con)));
format %{ "vadd_immL $dst, $src1, $con" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ vsetvli_helper(bt, Matcher::vector_length(this));
__ vadd_vi(as_VectorRegister($dst_src$$reg),
as_VectorRegister($dst_src$$reg),
__ vadd_vi(as_VectorRegister($dst$$reg),
as_VectorRegister($src1$$reg),
$con$$constant);
%}
ins_pipe(pipe_slow);
%}

// vector-scalar add (unpredicated)

instruct vadd_regI(vReg dst_src, iRegIorL2I src) %{
match(Set dst_src (AddVB dst_src (Replicate src)));
match(Set dst_src (AddVS dst_src (Replicate src)));
match(Set dst_src (AddVI dst_src (Replicate src)));
format %{ "vadd_regI $dst_src, $dst_src, $src" %}
instruct vadd_regI(vReg dst, vReg src1, iRegIorL2I src2) %{
match(Set dst (AddVB src1 (Replicate src2)));
match(Set dst (AddVS src1 (Replicate src2)));
match(Set dst (AddVI src1 (Replicate src2)));
format %{ "vadd_regI $dst, $src1, $src2" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ vsetvli_helper(bt, Matcher::vector_length(this));
__ vadd_vx(as_VectorRegister($dst_src$$reg),
as_VectorRegister($dst_src$$reg),
as_Register($src$$reg));
__ vadd_vx(as_VectorRegister($dst$$reg),
as_VectorRegister($src1$$reg),
as_Register($src2$$reg));
%}
ins_pipe(pipe_slow);
%}

instruct vadd_regL(vReg dst_src, iRegL src) %{
match(Set dst_src (AddVL dst_src (Replicate src)));
format %{ "vadd_regL $dst_src, $dst_src, $src" %}
instruct vadd_regL(vReg dst, vReg src1, iRegL src2) %{
match(Set dst (AddVL src1 (Replicate src2)));
format %{ "vadd_regL $dst, $src1, $src2" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ vsetvli_helper(bt, Matcher::vector_length(this));
__ vadd_vx(as_VectorRegister($dst_src$$reg),
as_VectorRegister($dst_src$$reg),
as_Register($src$$reg));
__ vadd_vx(as_VectorRegister($dst$$reg),
as_VectorRegister($src1$$reg),
as_Register($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
Expand Down Expand Up @@ -479,30 +479,30 @@ instruct vadd_immL_masked(vReg dst_src, immL5 con, vRegMask_V0 v0) %{

// vector-scalar add (predicated)

instruct vadd_regI_masked(vReg dst_src, iRegIorL2I src, vRegMask_V0 v0) %{
match(Set dst_src (AddVB (Binary dst_src (Replicate src)) v0));
match(Set dst_src (AddVS (Binary dst_src (Replicate src)) v0));
match(Set dst_src (AddVI (Binary dst_src (Replicate src)) v0));
format %{ "vadd_regI_masked $dst_src, $dst_src, $src" %}
instruct vadd_regI_masked(vReg dst_src, iRegIorL2I src2, vRegMask_V0 v0) %{
match(Set dst_src (AddVB (Binary dst_src (Replicate src2)) v0));
match(Set dst_src (AddVS (Binary dst_src (Replicate src2)) v0));
match(Set dst_src (AddVI (Binary dst_src (Replicate src2)) v0));
format %{ "vadd_regI_masked $dst_src, $dst_src, $src2" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ vsetvli_helper(bt, Matcher::vector_length(this));
__ vadd_vx(as_VectorRegister($dst_src$$reg),
as_VectorRegister($dst_src$$reg),
as_Register($src$$reg), Assembler::v0_t);
as_Register($src2$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}

instruct vadd_regL_masked(vReg dst_src, iRegL src, vRegMask_V0 v0) %{
match(Set dst_src (AddVL (Binary dst_src (Replicate src)) v0));
format %{ "vadd_regL_masked $dst_src, $dst_src, $src" %}
instruct vadd_regL_masked(vReg dst_src, iRegL src2, vRegMask_V0 v0) %{
match(Set dst_src (AddVL (Binary dst_src (Replicate src2)) v0));
format %{ "vadd_regL_masked $dst_src, $dst_src, $src2" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ vsetvli_helper(bt, Matcher::vector_length(this));
__ vadd_vx(as_VectorRegister($dst_src$$reg),
as_VectorRegister($dst_src$$reg),
as_Register($src$$reg), Assembler::v0_t);
as_Register($src2$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}
Expand Down Expand Up @@ -573,60 +573,60 @@ instruct vsub_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{

// vector-scalar sub (unpredicated)

instruct vsub_regI(vReg dst_src, iRegIorL2I src) %{
match(Set dst_src (SubVB dst_src (Replicate src)));
match(Set dst_src (SubVS dst_src (Replicate src)));
match(Set dst_src (SubVI dst_src (Replicate src)));
format %{ "vsub_regI $dst_src, $dst_src, $src" %}
instruct vsub_regI(vReg dst, vReg src1, iRegIorL2I src2) %{
match(Set dst (SubVB src1 (Replicate src2)));
match(Set dst (SubVS src1 (Replicate src2)));
match(Set dst (SubVI src1 (Replicate src2)));
format %{ "vsub_regI $dst, $src1, $src2" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ vsetvli_helper(bt, Matcher::vector_length(this));
__ vsub_vx(as_VectorRegister($dst_src$$reg),
as_VectorRegister($dst_src$$reg),
as_Register($src$$reg));
__ vsub_vx(as_VectorRegister($dst$$reg),
as_VectorRegister($src1$$reg),
as_Register($src2$$reg));
%}
ins_pipe(pipe_slow);
%}

instruct vsub_regL(vReg dst_src, iRegL src) %{
match(Set dst_src (SubVL dst_src (Replicate src)));
format %{ "vsub_regL $dst_src, $dst_src, $src" %}
instruct vsub_regL(vReg dst, vReg src1, iRegL src2) %{
match(Set dst (SubVL src1 (Replicate src2)));
format %{ "vsub_regL $dst, $src1, $src2" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ vsetvli_helper(bt, Matcher::vector_length(this));
__ vsub_vx(as_VectorRegister($dst_src$$reg),
as_VectorRegister($dst_src$$reg),
as_Register($src$$reg));
__ vsub_vx(as_VectorRegister($dst$$reg),
as_VectorRegister($src1$$reg),
as_Register($src2$$reg));
%}
ins_pipe(pipe_slow);
%}

// vector-scalar sub (predicated)

instruct vsub_regI_masked(vReg dst_src, iRegIorL2I src, vRegMask_V0 v0) %{
match(Set dst_src (SubVB (Binary dst_src (Replicate src)) v0));
match(Set dst_src (SubVS (Binary dst_src (Replicate src)) v0));
match(Set dst_src (SubVI (Binary dst_src (Replicate src)) v0));
format %{ "vsub_regI_masked $dst_src, $dst_src, $src" %}
instruct vsub_regI_masked(vReg dst_src, iRegIorL2I src2, vRegMask_V0 v0) %{
match(Set dst_src (SubVB (Binary dst_src (Replicate src2)) v0));
match(Set dst_src (SubVS (Binary dst_src (Replicate src2)) v0));
match(Set dst_src (SubVI (Binary dst_src (Replicate src2)) v0));
format %{ "vsub_regI_masked $dst_src, $dst_src, $src2" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ vsetvli_helper(bt, Matcher::vector_length(this));
__ vsub_vx(as_VectorRegister($dst_src$$reg),
as_VectorRegister($dst_src$$reg),
as_Register($src$$reg), Assembler::v0_t);
as_Register($src2$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}

instruct vsub_regL_masked(vReg dst_src, iRegL src, vRegMask_V0 v0) %{
match(Set dst_src (SubVL (Binary dst_src (Replicate src)) v0));
format %{ "vsub_regL_masked $dst_src, $dst_src, $src" %}
instruct vsub_regL_masked(vReg dst_src, iRegL src2, vRegMask_V0 v0) %{
match(Set dst_src (SubVL (Binary dst_src (Replicate src2)) v0));
format %{ "vsub_regL_masked $dst_src, $dst_src, $src2" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ vsetvli_helper(bt, Matcher::vector_length(this));
__ vsub_vx(as_VectorRegister($dst_src$$reg),
as_VectorRegister($dst_src$$reg),
as_Register($src$$reg), Assembler::v0_t);
as_Register($src2$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}
Expand Down Expand Up @@ -1649,60 +1649,60 @@ instruct vmul_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{

// vector-scalar mul (unpredicated)

instruct vmul_regI(vReg dst_src, iRegIorL2I src) %{
match(Set dst_src (MulVB dst_src (Replicate src)));
match(Set dst_src (MulVS dst_src (Replicate src)));
match(Set dst_src (MulVI dst_src (Replicate src)));
format %{ "vmul_regI $dst_src, $dst_src, $src" %}
instruct vmul_regI(vReg dst, vReg src1, iRegIorL2I src2) %{
match(Set dst (MulVB src1 (Replicate src2)));
match(Set dst (MulVS src1 (Replicate src2)));
match(Set dst (MulVI src1 (Replicate src2)));
format %{ "vmul_regI $dst, $src1, $src2" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ vsetvli_helper(bt, Matcher::vector_length(this));
__ vmul_vx(as_VectorRegister($dst_src$$reg),
as_VectorRegister($dst_src$$reg),
as_Register($src$$reg));
__ vmul_vx(as_VectorRegister($dst$$reg),
as_VectorRegister($src1$$reg),
as_Register($src2$$reg));
%}
ins_pipe(pipe_slow);
%}

instruct vmul_regL(vReg dst_src, iRegL src) %{
match(Set dst_src (MulVL dst_src (Replicate src)));
format %{ "vmul_regL $dst_src, $dst_src, $src" %}
instruct vmul_regL(vReg dst, vReg src1, iRegL src2) %{
match(Set dst (MulVL src1 (Replicate src2)));
format %{ "vmul_regL $dst, $src1, $src2" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ vsetvli_helper(bt, Matcher::vector_length(this));
__ vmul_vx(as_VectorRegister($dst_src$$reg),
as_VectorRegister($dst_src$$reg),
as_Register($src$$reg));
__ vmul_vx(as_VectorRegister($dst$$reg),
as_VectorRegister($src1$$reg),
as_Register($src2$$reg));
%}
ins_pipe(pipe_slow);
%}

// vector-scalar mul (predicated)

instruct vmul_regI_masked(vReg dst_src, iRegIorL2I src, vRegMask_V0 v0) %{
match(Set dst_src (MulVB (Binary dst_src (Replicate src)) v0));
match(Set dst_src (MulVS (Binary dst_src (Replicate src)) v0));
match(Set dst_src (MulVI (Binary dst_src (Replicate src)) v0));
format %{ "vmul_regI_masked $dst_src, $dst_src, $src" %}
instruct vmul_regI_masked(vReg dst_src, iRegIorL2I src2, vRegMask_V0 v0) %{
match(Set dst_src (MulVB (Binary dst_src (Replicate src2)) v0));
match(Set dst_src (MulVS (Binary dst_src (Replicate src2)) v0));
match(Set dst_src (MulVI (Binary dst_src (Replicate src2)) v0));
format %{ "vmul_regI_masked $dst_src, $dst_src, $src2" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ vsetvli_helper(bt, Matcher::vector_length(this));
__ vmul_vx(as_VectorRegister($dst_src$$reg),
as_VectorRegister($dst_src$$reg),
as_Register($src$$reg), Assembler::v0_t);
as_Register($src2$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}

instruct vmul_regL_masked(vReg dst_src, iRegL src, vRegMask_V0 v0) %{
match(Set dst_src (MulVL (Binary dst_src (Replicate src)) v0));
format %{ "vmul_regL_masked $dst_src, $dst_src, $src" %}
instruct vmul_regL_masked(vReg dst_src, iRegL src2, vRegMask_V0 v0) %{
match(Set dst_src (MulVL (Binary dst_src (Replicate src2)) v0));
format %{ "vmul_regL_masked $dst_src, $dst_src, $src2" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ vsetvli_helper(bt, Matcher::vector_length(this));
__ vmul_vx(as_VectorRegister($dst_src$$reg),
as_VectorRegister($dst_src$$reg),
as_Register($src$$reg), Assembler::v0_t);
as_Register($src2$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}
Expand Down

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