WIP: Modularize backends

.gitignore

@@ -1 +1,2 @@
 /target
+.vscode

Cargo.toml

@@ -27,4 +27,4 @@ serde_with = "2.0.1"                                 # for serializing arkworks
 serde_json = "1.0.85"                                # to (de)serialize JSON
 serde = "1.0.144"                                    # to (de)serialize objects
 thiserror = "1.0.31"                                 # helpful error traits
-toml = "0.8.8"                                       # to parse manifest files
+toml = "0.8.8"                                       # to parse manifest files

src/asm.rs

@@ -27,28 +27,24 @@ use std::hash::Hash;
 
 use itertools::Itertools;
 
+use crate::backends::Backend;
 use crate::circuit_writer::writer::AnnotatedCell;
-use crate::circuit_writer::{CircuitWriter, DebugInfo};
+use crate::circuit_writer::{CircuitWriter, DebugInfo, Gate};
 use crate::compiler::Sources;
-use crate::{
-    circuit_writer::{Gate, Wiring},
-    constants::{Field, Span},
-    helpers::PrettyField as _,
-};
+use crate::constants::{Field, Span};
+use crate::helpers::PrettyField;
 
-impl CircuitWriter {
+impl<B: Backend> CircuitWriter<B> {
     pub fn generate_asm(&self, sources: &Sources, debug: bool) -> String {
         let mut res = "".to_string();
 
         // version
         res.push_str("@ noname.0.7.0\n\n");
 
         // vars
-        let mut vars = OrderedHashSet::default();
+        let mut vars: OrderedHashSet<B::Field> = OrderedHashSet::default();
 
-        let gates = self.compiled_gates();
-
-        for Gate { coeffs, .. } in gates {
+        for Gate { coeffs, .. } in self.backend.gates() {
             extract_vars_from_coeffs(&mut vars, coeffs);
         }
 
@@ -65,9 +61,14 @@ impl CircuitWriter {
             title(&mut res, "GATES");
         }
 
-        for (row, (Gate { typ, coeffs }, debug_info)) in
-            gates.iter().zip(&self.debug_info).enumerate()
+        for (row, (Gate { typ, coeffs }, debug_info)) in self
+            .backend
+            .gates()
+            .iter()
+            .zip(self.backend.debug_info())
+            .enumerate()
         {
+            println!("gate {:?}", row);
             // gate #
             if debug {
                 writeln!(res, "╭{s}", s = "─".repeat(80)).unwrap();
@@ -83,7 +84,7 @@ impl CircuitWriter {
                 if !coeffs.is_empty() {
                     res.push('<');
                     res.push_str(&coeffs.join(","));
-                    res.push_str(">");
+                    res.push('>');
                 }
             }
 
@@ -107,25 +108,16 @@ impl CircuitWriter {
             title(&mut res, "WIRING");
         }
 
-        let mut cycles: Vec<_> = self
-            .wiring
-            .values()
-            .map(|w| match w {
-                Wiring::NotWired(_) => None,
-                Wiring::Wired(annotated_cells) => Some(annotated_cells),
-            })
-            .filter(Option::is_some)
-            .flatten()
-            .collect();
+        let mut cycles: Vec<_> = self.backend.wiring_cycles();
 
         // we must have a deterministic sort for the cycles,
         // otherwise the same circuit might have different representations
         cycles.sort();
 
         for annotated_cells in cycles {
             let (cells, debug_infos): (Vec<_>, Vec<_>) = annotated_cells
-                .into_iter()
-                .map(|AnnotatedCell { cell, debug }| (cell.clone(), debug.clone()))
+                .iter()
+                .map(|AnnotatedCell { cell, debug }| (*cell, debug.clone()))
                 .unzip();
 
             if debug {
@@ -143,8 +135,13 @@ impl CircuitWriter {
         res
     }
 
-    fn display_source(&self, res: &mut String, sources: &Sources, debug_infos: &[DebugInfo]) {
-        for DebugInfo { span, note } in debug_infos {
+    fn display_source(
+        &self,
+        res: &mut String,
+        sources: &crate::compiler::Sources,
+        debug_infos: &[DebugInfo],
+    ) {
+        for DebugInfo { span, note: _ } in debug_infos {
             // find filename and source
             let (file, source) = sources.get(&span.filename_id).expect("source not found");
 
@@ -177,7 +174,10 @@ impl CircuitWriter {
     }
 }
 
-fn extract_vars_from_coeffs(vars: &mut OrderedHashSet<Field>, coeffs: &[Field]) {
+pub fn extract_vars_from_coeffs<F: Field + PrettyField>(
+    vars: &mut OrderedHashSet<F>,
+    coeffs: &[F],
+) {
     for coeff in coeffs {
         let s = coeff.pretty();
         if s.len() >= 5 {
@@ -186,7 +186,7 @@ fn extract_vars_from_coeffs(vars: &mut OrderedHashSet<Field>, coeffs: &[Field])
     }
 }
 
-fn parse_coeffs(vars: &OrderedHashSet<Field>, coeffs: &[Field]) -> Vec<String> {
+fn parse_coeffs<F: Field + PrettyField>(vars: &OrderedHashSet<F>, coeffs: &[F]) -> Vec<String> {
     let mut coeffs: Vec<_> = coeffs
         .iter()
         .map(|x| {
@@ -287,7 +287,7 @@ uvwx
 yz
 ";
         assert_eq!(
-            find_exact_line(&SRC, Span::new(0, 5, 6)),
+            find_exact_line(SRC, Span::new(0, 5, 6)),
             (2, 5, "efgh\nijkl")
         );
     }