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@bbruce-c
bbruce-c authored Apr 26, 2022
1 parent 40da171 commit 087558a
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Showing 12 changed files with 1,823 additions and 25 deletions.
47 changes: 29 additions & 18 deletions Partial_sum_adder.sv
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Original file line number Diff line number Diff line change
@@ -1,29 +1,26 @@
//unfinished
`timescale 1ns/100ps
import SystemVerilogCSP::*;
module Partial_sum_adder (
interface in,
interface out
);
module Partial_sum_adder (interface in,out);
parameter adder_number=2'b00; //00--adder1,01--adder2,10--adder3
parameter adder3_num=2'b10;
parameter WIDTH=34;
parameter memb_p_WIDTH=8;
parameter threshold=64;
parameter PE1_addr=4'b1000;
parameter PE2_addr=4'b1001;
parameter threshold=16;
parameter PE1_addr=4'b0010;
parameter PE2_addr=4'b0110;
parameter PE3_addr=4'b1010;
parameter Adder_addr=4'b0110;
parameter Mem_addr=4'b0000;
parameter WR_addr=4'b0001;
parameter WR_addr=4'b0000;
parameter Out_to_Mem_zeros={20{1'b0}};
parameter MP_to_Mem_zeros={16{1'b0}};
parameter count_number=2'b10;
parameter done_singal=4'b1111;
parameter mem_p_type=2'b10;
parameter output_spike_type=2'b11;
logic [WIDTH-1:0] value;
logic [memb_p_WIDTH-1:0] partial_PE1,partial_PE2,partial_PE3,membrane_potential;
reg [memb_p_WIDTH-1:0] partial_PE1,partial_PE2,partial_PE3,membrane_potential;
logic output_spike;
logic [WIDTH-1:0] out_packet;
logic [3:0]output_spike_addr;
Expand Down Expand Up @@ -68,6 +65,7 @@ begin
begin
partial_PE1=value[7:0];
//flag_PE1_received=1;//count=count+1;
$display("firstRe---if--partial_PE1=%b",partial_PE1);
end

if (value[WIDTH-1:WIDTH-4]==PE2_addr) //src_addr=PE2
Expand All @@ -85,6 +83,7 @@ begin
begin
membrane_potential=value[WIDTH-27:WIDTH-34];
end
$display("%m first receive----packet:%b",value);


//second receive
Expand All @@ -93,6 +92,7 @@ begin
begin
partial_PE1=value[7:0];
//flag_PE1_received=1;//count=count+1;
//$display("secondRe---if--partial_PE1=%b",partial_PE1);
end

if (value[WIDTH-1:WIDTH-4]==PE2_addr) //PE2
Expand All @@ -110,12 +110,14 @@ begin
begin
membrane_potential=value[WIDTH-27:WIDTH-34];
end
$display("%m second receive----packet:%b",value);

//third receive
in.Receive(value);//PE3
if (value[WIDTH-1:WIDTH-4]==PE1_addr) //src_addr=PE1_addr
begin
partial_PE1=value[7:0];
//$display("thirdRe---if--partial_PE1=%b",partial_PE1);
//flag_PE1_received=1;//count=count+1;
end

Expand All @@ -135,6 +137,7 @@ begin
begin
membrane_potential=value[WIDTH-27:WIDTH-34];
end
$display("%m third receive----packet:%b",value);
//-----------------------------------------------------------------------------------------------


Expand All @@ -146,6 +149,7 @@ begin
if (value[WIDTH-1:WIDTH-4]==PE1_addr) //src_addr=PE1_addr
begin
partial_PE1=value[7:0];
//$display("forthRe---if--partial_PE1=%b",partial_PE1);
//flag_PE1_received=1;//count=count+1;
end

Expand All @@ -163,18 +167,23 @@ begin
if(value[WIDTH-1:WIDTH-4]==WR_addr)//src addr=WR_addr
if(value[WIDTH-9:WIDTH-10]==mem_p_type)//type=mem_p_type
begin
membrane_potential=value[WIDTH-27:WIDTH-34];
membrane_potential=value[WIDTH-27:WIDTH-34];//34-27=7:0
end
$display("partial_PE1:%b---partial_PE2:%b---partial_PE3:%b---mem_p:%b",partial_PE1,partial_PE2,partial_PE3,membrane_potential);
membrane_potential=partial_PE1+partial_PE2+partial_PE3+membrane_potential;
end
//$display("partial_PE1:%b---partial_PE2:%b---partial_PE3:%b---mem_p:%b",partial_PE1,partial_PE2,partial_PE3,membrane_potential);
$display("%m forth receive----packet:%b",value);
end


else //first input map
begin
membrane_potential=partial_PE1+partial_PE2+partial_PE3;
$display("partial_PE1:%b---partial_PE2:%b---partial_PE3:%b---",partial_PE1,partial_PE2,partial_PE3);
end

//generate output_spike 1-bit
if (membrane_potential>threshold)
if (membrane_potential>=threshold)
begin
output_spike=1;
membrane_potential=membrane_potential-threshold;
Expand All @@ -184,25 +193,27 @@ begin
output_spike=0;
end


//$display("partial_PE1:%b---partial_PE2:%b---partial_PE3:%b---",partial_PE1,partial_PE2,partial_PE3);
out_packet={Adder_addr,Mem_addr,mem_p_type,MP_to_Mem_zeros,membrane_potential};
$display("Membrane_P after compare%b",out_packet);
$display("add_num:%m---Membrane_P after compare%b",out_packet);
//4+4+2+16*zeros+8bits
//mem_p_type=10
out.Send(out_packet);
if (output_spike==1)
begin
output_spike_addr={adder_number,count};//row-col
output_spike_addr={count,adder_number};//row-col
out_packet={Adder_addr,Mem_addr,output_spike_type,Out_to_Mem_zeros,output_spike_addr};//4+4+22+4
//output_spike_type=10
$display("output_spike no_zero_send:%b",out_packet);
$display("add_num:%m---output_spike no_zero_send:%b,row:%b---col:%b",out_packet,count,adder_number);
out.Send(out_packet);
end
if (adder_number==adder3_num)//every time when adder3 finish calculating, send done_singal
begin
output_spike_addr=done_singal;
out_packet={Adder_addr,Mem_addr,output_spike_type,Out_to_Mem_zeros,output_spike_addr};
//output_spike_addr=done_singal;
//out_packet={Adder_addr,Mem_addr,output_spike_type,Out_to_Mem_zeros,output_spike_addr};
out_packet={Adder_addr,Mem_addr,output_spike_type,Out_to_Mem_zeros,done_singal};
out.Send(out_packet);//send done_singal
$display("add_num:%m---Done signal Sent!!!");
end
/***if (count==count_number)//count=2'b10
begin
Expand Down
208 changes: 208 additions & 0 deletions SNN_Accelerator123.sv
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Original file line number Diff line number Diff line change
@@ -0,0 +1,208 @@
`timescale 1ns/1ps
import SystemVerilogCSP::*;
module SNN_Accelerator123;
parameter WIDTH=34;
parameter FL=2;
parameter BL=1;
parameter x1=2'b00;
parameter x2=2'b01;
parameter x3=2'b10;
parameter y1=2'b00;
parameter y2=2'b01;
parameter y3=2'b10;
parameter adder1_num=2'b00;
parameter adder2_num=2'b01;
parameter adder3_num=2'b10;
parameter Adder1_addr=4'b0001;
parameter Adder2_addr=4'b0101;
parameter Adder3_addr=4'b1001;

Channel #(.hsProtocol(P4PhaseBD),.WIDTH(34)) intf [49:0] ();


router #(.WIDTH(WIDTH),
.FL(FL),
.BL(BL),
.Xaddr(x1),
.Yaddr(y1))
router1 (.N_in(intf[49]),
.N_out(intf[49]),
.S_in(intf[5]),
.S_out(intf[4]),
.E_in(intf[1]),
.E_out(intf[0]),
.W_in(intf[49]),
.W_out(intf[49]),
.P_in(intf[3]),
.P_out(intf[2]));


router #(.WIDTH(WIDTH),
.FL(FL),
.BL(BL),
.Xaddr(x2),
.Yaddr(y1))
router2 (.N_in(intf[49]),
.N_out(intf[49]),
.S_in(intf[11]),
.S_out(intf[10]),
.E_in(intf[7]),
.E_out(intf[6]),
.W_in(intf[0]),
.W_out(intf[1]),
.P_in(intf[9]),
.P_out(intf[8]));



router #(.WIDTH(WIDTH),
.FL(FL),
.BL(BL),
.Xaddr(x3),
.Yaddr(y1))
router3 (.N_in(intf[49]),
.N_out(intf[49]),
.S_in(intf[22]),
.S_out(intf[21]),
.E_in(intf[49]),
.E_out(intf[49]),
.W_in(intf[6]),
.W_out(intf[7]),
.P_in(intf[20]),
.P_out(intf[19]));

router #(.WIDTH(WIDTH),
.FL(FL),
.BL(BL),
.Xaddr(x1),
.Yaddr(y2))
router4 (.N_in(intf[4]),
.N_out(intf[5]),
.S_in(intf[28]),
.S_out(intf[27]),
.E_in(intf[24]),
.E_out(intf[23]),
.W_in(intf[49]),
.W_out(intf[49]),
.P_in(intf[26]),
.P_out(intf[25]));


router #(.WIDTH(WIDTH),
.FL(FL),
.BL(BL),
.Xaddr(x2),
.Yaddr(y2))
router5 (.N_in(intf[10]),
.N_out(intf[11]),
.S_in(intf[34]),
.S_out(intf[33]),
.E_in(intf[30]),
.E_out(intf[29]),
.W_in(intf[23]),
.W_out(intf[24]),
.P_in(intf[32]),
.P_out(intf[31]));


router #(.WIDTH(WIDTH),
.FL(FL),
.BL(BL),
.Xaddr(x3),
.Yaddr(y2))
router6 (.N_in(intf[21]),
.N_out(intf[22]),
.S_in(intf[38]),
.S_out(intf[37]),
.E_in(intf[49]),
.E_out(intf[49]),
.W_in(intf[29]),
.W_out(intf[30]),
.P_in(intf[36]),
.P_out(intf[35]));


router #(.WIDTH(WIDTH),
.FL(FL),
.BL(BL),
.Xaddr(x1),
.Yaddr(y3))
router7 (.N_in(intf[27]),
.N_out(intf[28]),
.S_in(intf[49]),
.S_out(intf[49]),
.E_in(intf[40]),
.E_out(intf[39]),
.W_in(intf[49]),
.W_out(intf[49]),
.P_in(intf[42]),
.P_out(intf[41]));

router #(.WIDTH(WIDTH),
.FL(FL),
.BL(BL),
.Xaddr(x2),
.Yaddr(y3))
router8 (.N_in(intf[33]),
.N_out(intf[34]),
.S_in(intf[49]),
.S_out(intf[49]),
.E_in(intf[44]),
.E_out(intf[43]),
.W_in(intf[39]),
.W_out(intf[40]),
.P_in(intf[46]),
.P_out(intf[45]));

router #(.WIDTH(WIDTH),
.FL(FL),
.BL(BL),
.Xaddr(x3),
.Yaddr(y3))
router9 (.N_in(intf[37]),
.N_out(intf[38]),
.S_in(intf[49]),
.S_out(intf[49]),
.E_in(intf[49]),
.E_out(intf[49]),
.W_in(intf[43]),
.W_out(intf[44]),
.P_in(intf[48]),
.P_out(intf[47]));



memory_wrapper memory_wrapper1(.toMemRead(intf[12]), .toMemWrite(intf[13]),
.toMemT(intf[14]),
.toMemX(intf[15]),.toMemY(intf[16]),
.toMemSendData(intf[17]),
.fromMemGetData(intf[18]),
.toNOC(intf[3]),.fromNOC(intf[2]));
memory memory1(.read(intf[12]),
.write(intf[13]),
.T(intf[14]),
.x(intf[15]),
.y(intf[16]),
.data_out(intf[18]),
.data_in(intf[17]));
data_bucket db1 (.r(intf[8]));
data_bucket db2 (.r(intf[19]));
Partial_sum_adder #(.adder_number(adder1_num),.Adder_addr(Adder1_addr))
adder1 (.in(intf[25]),.out(intf[26]));
Partial_sum_adder #(.adder_number(adder2_num),.Adder_addr(Adder2_addr))
adder2(.in(intf[31]),.out(intf[32]));
Partial_sum_adder #(.adder_number(adder3_num),.Adder_addr(Adder3_addr))
adder3(.in(intf[35]),.out(intf[36]));
pe pe1(.packet_in(intf[41]),.packet_out(intf[42]));
pe pe2(.packet_in(intf[45]),.packet_out(intf[46]));
pe pe3(.packet_in(intf[47]),.packet_out(intf[48]));

initial begin
#20000;
$stop;


end
endmodule


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