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1. Asynchronous_fifo Asynchronous_fifo Public

   Async Fifo Design in Verilog/RTL

   Verilog

2. Fast_to_Slow_CDC Fast_to_Slow_CDC Public

   A VHDL implementation of a Clock Domain Crossing (CDC) example that transfers a signal from a fast clock domain to a slower clock domain. This project includes customizable parameters for the slow …

   VHDL